From 14137fe1e078d1eda7bf923ec1268e9f0c789c9a Mon Sep 17 00:00:00 2001
From: Johannes Stoelp <johannes.stoelp@gmail.com>
Date: Wed, 9 Apr 2025 23:48:02 +0200
Subject: nginx: intel vol4

---
 roles/webserver/files/www/memzero/pub/.gen.sh         | 1 +
 roles/webserver/files/www/memzero/pub/references.html | 4 ++++
 2 files changed, 5 insertions(+)

(limited to 'roles/webserver/files/www/memzero/pub')

diff --git a/roles/webserver/files/www/memzero/pub/.gen.sh b/roles/webserver/files/www/memzero/pub/.gen.sh
index 6131b8d..f591ddd 100644
--- a/roles/webserver/files/www/memzero/pub/.gen.sh
+++ b/roles/webserver/files/www/memzero/pub/.gen.sh
@@ -110,6 +110,7 @@ emit "x86" arch/intel/intel64-optimization-ref-vol2.pdf    https://cdrdv2.intel.
 emit "x86" arch/intel/intel64-vol1-architecture-manual.pdf https://cdrdv2.intel.com/v1/dl/getContent/671436
 emit "x86" arch/intel/intel64-vol2-instruction-ref.pdf     https://cdrdv2.intel.com/v1/dl/getContent/671110
 emit "x86" arch/intel/intel64-vol3-system-programming.pdf  https://cdrdv2.intel.com/v1/dl/getContent/671447
+emit "x86" arch/intel/intel64-vol4-msr-registers.pdf       https://cdrdv2.intel.com/v1/dl/getContent/671098
 
 emit "riscv" arch/riscv/rv-1-unprivileged-isa.pdf        https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC
 emit "riscv" arch/riscv/rv-2-privileged-architecture.pdf https://github.com/riscv/riscv-isa-manual/releases/tag/Priv-v1.12
diff --git a/roles/webserver/files/www/memzero/pub/references.html b/roles/webserver/files/www/memzero/pub/references.html
index 4577e79..8beb69d 100644
--- a/roles/webserver/files/www/memzero/pub/references.html
+++ b/roles/webserver/files/www/memzero/pub/references.html
@@ -125,6 +125,10 @@
       <a style="color:black;" href="/pub/arch/intel/intel64-vol3-system-programming.pdf">arch/intel/intel64-vol3-system-programming.pdf</a>
       [<a href="https://cdrdv2.intel.com/v1/dl/getContent/671447">original</a>]
     </li>
+    <li class="content x86">
+      <a style="color:black;" href="/pub/arch/intel/intel64-vol4-msr-registers.pdf">arch/intel/intel64-vol4-msr-registers.pdf</a>
+      [<a href="https://cdrdv2.intel.com/v1/dl/getContent/671098">original</a>]
+    </li>
     <li class="content riscv">
       <a style="color:black;" href="/pub/arch/riscv/rv-1-unprivileged-isa.pdf">arch/riscv/rv-1-unprivileged-isa.pdf</a>
       [<a href="https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC">original</a>]
-- 
cgit v1.2.3