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<a href="#428" id="428">428</a></pre></div><pre class="rust"><code><span class="doccomment">//! The `x64` jit assembler.
</span><span class="kw">use </span><span class="kw">crate</span>::imm::Imm;
<span class="kw">use </span><span class="kw">crate</span>::mem::{AddrMode, Mem, Mem16, Mem32, Mem64, Mem8};
<span class="kw">use </span><span class="kw">crate</span>::reg::{Reg, Reg16, Reg32, Reg64, Reg8};
<span class="kw">use </span><span class="kw">crate</span>::Label;
<span class="doccomment">/// Encode the `REX` byte.
</span><span class="kw">const fn </span>rex(w: bool, r: u8, x: u8, b: u8) -> u8 {
<span class="kw">let </span>w = <span class="kw">if </span>w { <span class="number">1 </span>} <span class="kw">else </span>{ <span class="number">0 </span>};
<span class="kw">let </span>r = (r >> <span class="number">3</span>) & <span class="number">1</span>;
<span class="kw">let </span>x = (x >> <span class="number">3</span>) & <span class="number">1</span>;
<span class="kw">let </span>b = (b >> <span class="number">3</span>) & <span class="number">1</span>;
<span class="number">0b0100_0000 </span>| ((w & <span class="number">1</span>) << <span class="number">3</span>) | (r << <span class="number">2</span>) | (x << <span class="number">1</span>) | b
}
<span class="doccomment">/// Encode the `ModR/M` byte.
</span><span class="kw">const fn </span>modrm(mod_: u8, reg: u8, rm: u8) -> u8 {
((mod_ & <span class="number">0b11</span>) << <span class="number">6</span>) | ((reg & <span class="number">0b111</span>) << <span class="number">3</span>) | (rm & <span class="number">0b111</span>)
}
<span class="doccomment">/// Encode the `SIB` byte.
</span><span class="kw">const fn </span>sib(scale: u8, index: u8, base: u8) -> u8 {
((scale & <span class="number">0b11</span>) << <span class="number">6</span>) | ((index & <span class="number">0b111</span>) << <span class="number">3</span>) | (base & <span class="number">0b111</span>)
}
<span class="doccomment">/// `x64` jit assembler.
</span><span class="kw">pub struct </span>Asm {
buf: Vec<u8>,
}
<span class="kw">impl </span>Asm {
<span class="doccomment">/// Create a new `x64` jit assembler.
</span><span class="kw">pub fn </span>new() -> Asm {
<span class="comment">// Some random default capacity.
</span><span class="kw">let </span>buf = Vec::with_capacity(<span class="number">1024</span>);
Asm { buf }
}
<span class="doccomment">/// Consume the assembler and get the emitted code.
</span><span class="kw">pub fn </span>into_code(<span class="self">self</span>) -> Vec<u8> {
<span class="self">self</span>.buf
}
<span class="doccomment">/// Emit a slice of bytes.
</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>emit(<span class="kw-2">&mut </span><span class="self">self</span>, bytes: <span class="kw-2">&</span>[u8]) {
<span class="self">self</span>.buf.extend_from_slice(bytes);
}
<span class="doccomment">/// Emit a slice of optional bytes.
</span><span class="kw">fn </span>emit_optional(<span class="kw-2">&mut </span><span class="self">self</span>, bytes: <span class="kw-2">&</span>[<span class="prelude-ty">Option</span><u8>]) {
<span class="kw">for </span>byte <span class="kw">in </span>bytes.iter().filter_map(|<span class="kw-2">&</span>b| b) {
<span class="self">self</span>.buf.push(byte);
}
}
<span class="doccomment">/// Emit a slice of bytes at `pos`.
///
/// # Panics
///
/// Panics if [pos..pos+len] indexes out of bound of the underlying code buffer.
</span><span class="kw">fn </span>emit_at(<span class="kw-2">&mut </span><span class="self">self</span>, pos: usize, bytes: <span class="kw-2">&</span>[u8]) {
<span class="kw">if let </span><span class="prelude-val">Some</span>(buf) = <span class="self">self</span>.buf.get_mut(pos..pos + bytes.len()) {
buf.copy_from_slice(bytes);
} <span class="kw">else </span>{
<span class="macro">unimplemented!</span>();
}
}
<span class="doccomment">/// Bind the [Label] to the current location.
</span><span class="kw">pub fn </span>bind(<span class="kw-2">&mut </span><span class="self">self</span>, label: <span class="kw-2">&mut </span>Label) {
<span class="comment">// Bind the label to the current offset.
</span>label.bind(<span class="self">self</span>.buf.len());
<span class="comment">// Resolve any pending relocations for the label.
</span><span class="self">self</span>.resolve(label);
}
<span class="doccomment">/// If the [Label] is bound, patch any pending relocation.
</span><span class="kw">fn </span>resolve(<span class="kw-2">&mut </span><span class="self">self</span>, label: <span class="kw-2">&mut </span>Label) {
<span class="kw">if let </span><span class="prelude-val">Some</span>(loc) = label.location() {
<span class="comment">// For now we only support disp32 as label location.
</span><span class="kw">let </span>loc = i32::try_from(loc).expect(<span class="string">"Label location did not fit into i32."</span>);
<span class="comment">// Resolve any pending relocations for the label.
</span><span class="kw">for </span>off <span class="kw">in </span>label.offsets_mut().drain() {
<span class="comment">// Displacement is relative to the next instruction following the jump.
// We record the offset to patch at the first byte of the disp32 therefore we need
// to account for that in the disp computation.
</span><span class="kw">let </span>disp32 = loc - i32::try_from(off).expect(<span class="string">"Label offset did not fit into i32"</span>) - <span class="number">4 </span><span class="comment">/* account for the disp32 */</span>;
<span class="comment">// Patch the relocation with the disp32.
</span><span class="self">self</span>.emit_at(off, <span class="kw-2">&</span>disp32.to_ne_bytes());
}
}
}
<span class="comment">// -- Encode utilities.
</span><span class="doccomment">/// Encode an register-register instruction.
</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_rr<T: Reg>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: <span class="kw-2">&</span>[u8], op1: T, op2: T)
<span class="kw">where
</span><span class="self">Self</span>: EncodeRR<T>,
{
<span class="comment">// MR operand encoding.
// op1 -> modrm.rm
// op2 -> modrm.reg
</span><span class="kw">let </span>modrm = modrm(
<span class="number">0b11</span>, <span class="comment">/* mod */
</span>op2.idx(), <span class="comment">/* reg */
</span>op1.idx(), <span class="comment">/* rm */
</span>);
<span class="kw">let </span>prefix = <<span class="self">Self </span><span class="kw">as </span>EncodeRR<T>>::legacy_prefix();
<span class="kw">let </span>rex = <<span class="self">Self </span><span class="kw">as </span>EncodeRR<T>>::rex(op1, op2);
<span class="self">self</span>.emit_optional(<span class="kw-2">&</span>[prefix, rex]);
<span class="self">self</span>.emit(opc);
<span class="self">self</span>.emit(<span class="kw-2">&</span>[modrm]);
}
<span class="doccomment">/// Encode an offset-immediate instruction.
/// Register idx is encoded in the opcode.
</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_oi<T: Reg, U: Imm>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, op1: T, op2: U)
<span class="kw">where
</span><span class="self">Self</span>: EncodeR<T>,
{
<span class="kw">let </span>opc = opc + (op1.idx() & <span class="number">0b111</span>);
<span class="kw">let </span>prefix = <<span class="self">Self </span><span class="kw">as </span>EncodeR<T>>::legacy_prefix();
<span class="kw">let </span>rex = <<span class="self">Self </span><span class="kw">as </span>EncodeR<T>>::rex(op1);
<span class="self">self</span>.emit_optional(<span class="kw-2">&</span>[prefix, rex]);
<span class="self">self</span>.emit(<span class="kw-2">&</span>[opc]);
<span class="self">self</span>.emit(op2.bytes());
}
<span class="doccomment">/// Encode a register instruction.
</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_r<T: Reg>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, opc_ext: u8, op1: T)
<span class="kw">where
</span><span class="self">Self</span>: EncodeR<T>,
{
<span class="comment">// M operand encoding.
// op1 -> modrm.rm
// opc extension -> modrm.reg
</span><span class="kw">let </span>modrm = modrm(
<span class="number">0b11</span>, <span class="comment">/* mod */
</span>opc_ext, <span class="comment">/* reg */
</span>op1.idx(), <span class="comment">/* rm */
</span>);
<span class="kw">let </span>prefix = <<span class="self">Self </span><span class="kw">as </span>EncodeR<T>>::legacy_prefix();
<span class="kw">let </span>rex = <<span class="self">Self </span><span class="kw">as </span>EncodeR<T>>::rex(op1);
<span class="self">self</span>.emit_optional(<span class="kw-2">&</span>[prefix, rex]);
<span class="self">self</span>.emit(<span class="kw-2">&</span>[opc, modrm]);
}
<span class="doccomment">/// Encode a memory operand instruction.
</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_m<T: Mem>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, opc_ext: u8, op1: T)
<span class="kw">where
</span><span class="self">Self</span>: EncodeM<T>,
{
<span class="comment">// M operand encoding.
// op1 -> modrm.rm
</span><span class="kw">let </span>(mode, rm) = <span class="kw">match </span>op1.mode() {
AddrMode::Indirect => {
<span class="macro">assert!</span>(!op1.base().need_sib() && !op1.base().is_pc_rel());
(<span class="number">0b00</span>, op1.base().idx())
}
AddrMode::IndirectDisp => {
<span class="macro">assert!</span>(!op1.base().need_sib());
(<span class="number">0b10</span>, op1.base().idx())
}
AddrMode::IndirectBaseIndex => {
<span class="macro">assert!</span>(!op1.base().is_pc_rel());
<span class="comment">// Using rsp as index register is interpreted as just base w/o offset.
// https://wiki.osdev.org/X86-64_Instruction_Encoding#32.2F64-bit_addressing_2
// Disallow this case, as guard for the user.
</span><span class="macro">assert!</span>(!<span class="macro">matches!</span>(op1.index(), Reg64::rsp));
(<span class="number">0b00</span>, <span class="number">0b100</span>)
}
};
<span class="kw">let </span>modrm = modrm(
mode, <span class="comment">/* mode */
</span>opc_ext, <span class="comment">/* reg */
</span>rm, <span class="comment">/* rm */
</span>);
<span class="kw">let </span>prefix = <<span class="self">Self </span><span class="kw">as </span>EncodeM<T>>::legacy_prefix();
<span class="kw">let </span>rex = <<span class="self">Self </span><span class="kw">as </span>EncodeM<T>>::rex(<span class="kw-2">&</span>op1);
<span class="self">self</span>.emit_optional(<span class="kw-2">&</span>[prefix, rex]);
<span class="self">self</span>.emit(<span class="kw-2">&</span>[opc, modrm]);
<span class="kw">match </span>op1.mode() {
AddrMode::Indirect => {}
AddrMode::IndirectDisp => <span class="self">self</span>.emit(<span class="kw-2">&</span>op1.disp().to_ne_bytes()),
AddrMode::IndirectBaseIndex => {
<span class="self">self</span>.emit(<span class="kw-2">&</span>[sib(<span class="number">0</span>, op1.index().idx(), op1.base().idx())])
}
}
}
<span class="doccomment">/// Encode a memory-immediate instruction.
</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_mi<M: Mem, T: Imm>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, opc_ext: u8, op1: M, op2: T)
<span class="kw">where
</span><span class="self">Self</span>: EncodeM<M>,
{
<span class="comment">// MI operand encoding.
// op1 -> modrm.rm
// op2 -> imm
</span><span class="kw">let </span>(mode, rm) = <span class="kw">match </span>op1.mode() {
AddrMode::Indirect => {
<span class="macro">assert!</span>(!op1.base().need_sib() && !op1.base().is_pc_rel());
(<span class="number">0b00</span>, op1.base().idx())
}
AddrMode::IndirectDisp => {
<span class="macro">assert!</span>(!op1.base().need_sib());
(<span class="number">0b10</span>, op1.base().idx())
}
AddrMode::IndirectBaseIndex => {
<span class="macro">assert!</span>(!op1.base().is_pc_rel());
<span class="comment">// Using rsp as index register is interpreted as just base w/o offset.
// https://wiki.osdev.org/X86-64_Instruction_Encoding#32.2F64-bit_addressing_2
// Disallow this case, as guard for the user.
</span><span class="macro">assert!</span>(!<span class="macro">matches!</span>(op1.index(), Reg64::rsp));
(<span class="number">0b00</span>, <span class="number">0b100</span>)
}
};
<span class="kw">let </span>modrm = modrm(
mode, <span class="comment">/* mode */
</span>opc_ext, <span class="comment">/* reg */
</span>rm, <span class="comment">/* rm */
</span>);
<span class="kw">let </span>prefix = <<span class="self">Self </span><span class="kw">as </span>EncodeM<M>>::legacy_prefix();
<span class="kw">let </span>rex = <<span class="self">Self </span><span class="kw">as </span>EncodeM<M>>::rex(<span class="kw-2">&</span>op1);
<span class="self">self</span>.emit_optional(<span class="kw-2">&</span>[prefix, rex]);
<span class="self">self</span>.emit(<span class="kw-2">&</span>[opc, modrm]);
<span class="kw">match </span>op1.mode() {
AddrMode::Indirect => {}
AddrMode::IndirectDisp => <span class="self">self</span>.emit(<span class="kw-2">&</span>op1.disp().to_ne_bytes()),
AddrMode::IndirectBaseIndex => {
<span class="self">self</span>.emit(<span class="kw-2">&</span>[sib(<span class="number">0</span>, op1.index().idx(), op1.base().idx())])
}
}
<span class="self">self</span>.emit(op2.bytes());
}
<span class="doccomment">/// Encode a memory-register instruction.
</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_mr<M: Mem, T: Reg>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, op1: M, op2: T)
<span class="kw">where
</span><span class="self">Self</span>: EncodeMR<M>,
{
<span class="comment">// MR operand encoding.
// op1 -> modrm.rm
// op2 -> modrm.reg
</span><span class="kw">let </span>(mode, rm) = <span class="kw">match </span>op1.mode() {
AddrMode::Indirect => {
<span class="macro">assert!</span>(!op1.base().need_sib() && !op1.base().is_pc_rel());
(<span class="number">0b00</span>, op1.base().idx())
}
AddrMode::IndirectDisp => {
<span class="macro">assert!</span>(!op1.base().need_sib());
(<span class="number">0b10</span>, op1.base().idx())
}
AddrMode::IndirectBaseIndex => {
<span class="macro">assert!</span>(!op1.base().is_pc_rel());
<span class="comment">// Using rsp as index register is interpreted as just base w/o offset.
// https://wiki.osdev.org/X86-64_Instruction_Encoding#32.2F64-bit_addressing_2
// Disallow this case, as guard for the user.
</span><span class="macro">assert!</span>(!<span class="macro">matches!</span>(op1.index(), Reg64::rsp));
(<span class="number">0b00</span>, <span class="number">0b100</span>)
}
};
<span class="kw">let </span>modrm = modrm(
mode, <span class="comment">/* mode */
</span>op2.idx(), <span class="comment">/* reg */
</span>rm, <span class="comment">/* rm */
</span>);
<span class="kw">let </span>prefix = <<span class="self">Self </span><span class="kw">as </span>EncodeMR<M>>::legacy_prefix();
<span class="kw">let </span>rex = <<span class="self">Self </span><span class="kw">as </span>EncodeMR<M>>::rex(<span class="kw-2">&</span>op1, op2);
<span class="self">self</span>.emit_optional(<span class="kw-2">&</span>[prefix, rex]);
<span class="self">self</span>.emit(<span class="kw-2">&</span>[opc, modrm]);
<span class="kw">match </span>op1.mode() {
AddrMode::Indirect => {}
AddrMode::IndirectDisp => <span class="self">self</span>.emit(<span class="kw-2">&</span>op1.disp().to_ne_bytes()),
AddrMode::IndirectBaseIndex => {
<span class="self">self</span>.emit(<span class="kw-2">&</span>[sib(<span class="number">0</span>, op1.index().idx(), op1.base().idx())])
}
}
}
<span class="doccomment">/// Encode a register-memory instruction.
</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_rm<T: Reg, M: Mem>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, op1: T, op2: M)
<span class="kw">where
</span><span class="self">Self</span>: EncodeMR<M>,
{
<span class="comment">// RM operand encoding.
// op1 -> modrm.reg
// op2 -> modrm.rm
</span><span class="self">self</span>.encode_mr(opc, op2, op1);
}
<span class="doccomment">/// Encode a jump to label instruction.
</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_jmp_label(<span class="kw-2">&mut </span><span class="self">self</span>, opc: <span class="kw-2">&</span>[u8], op1: <span class="kw-2">&mut </span>Label) {
<span class="comment">// Emit the opcode.
</span><span class="self">self</span>.emit(opc);
<span class="comment">// Record relocation offset starting at the first byte of the disp32.
</span>op1.record_offset(<span class="self">self</span>.buf.len());
<span class="comment">// Emit a zeroed disp32, which serves as placeholder for the relocation.
// We currently only support disp32 jump targets.
</span><span class="self">self</span>.emit(<span class="kw-2">&</span>[<span class="number">0u8</span>; <span class="number">4</span>]);
<span class="comment">// Resolve any pending relocations for the label.
</span><span class="self">self</span>.resolve(op1);
}
}
<span class="comment">// -- Encoder helper.
</span><span class="doccomment">/// Encode helper for register-register instructions.
</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">trait </span>EncodeRR<T: Reg> {
<span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> {
<span class="prelude-val">None
</span>}
<span class="kw">fn </span>rex(op1: T, op2: T) -> <span class="prelude-ty">Option</span><u8> {
<span class="kw">if </span>op1.need_rex() || op2.need_rex() {
<span class="prelude-val">Some</span>(rex(op1.rexw(), op2.idx(), <span class="number">0</span>, op1.idx()))
} <span class="kw">else </span>{
<span class="prelude-val">None
</span>}
}
}
<span class="kw">impl </span>EncodeRR<Reg8> <span class="kw">for </span>Asm {}
<span class="kw">impl </span>EncodeRR<Reg32> <span class="kw">for </span>Asm {}
<span class="kw">impl </span>EncodeRR<Reg16> <span class="kw">for </span>Asm {
<span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> {
<span class="prelude-val">Some</span>(<span class="number">0x66</span>)
}
}
<span class="kw">impl </span>EncodeRR<Reg64> <span class="kw">for </span>Asm {}
<span class="doccomment">/// Encode helper for register instructions.
</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">trait </span>EncodeR<T: Reg> {
<span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> {
<span class="prelude-val">None
</span>}
<span class="kw">fn </span>rex(op1: T) -> <span class="prelude-ty">Option</span><u8> {
<span class="kw">if </span>op1.need_rex() {
<span class="prelude-val">Some</span>(rex(op1.rexw(), <span class="number">0</span>, <span class="number">0</span>, op1.idx()))
} <span class="kw">else </span>{
<span class="prelude-val">None
</span>}
}
}
<span class="kw">impl </span>EncodeR<Reg8> <span class="kw">for </span>Asm {}
<span class="kw">impl </span>EncodeR<Reg32> <span class="kw">for </span>Asm {}
<span class="kw">impl </span>EncodeR<Reg16> <span class="kw">for </span>Asm {
<span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> {
<span class="prelude-val">Some</span>(<span class="number">0x66</span>)
}
}
<span class="kw">impl </span>EncodeR<Reg64> <span class="kw">for </span>Asm {}
<span class="doccomment">/// Encode helper for memory-register instructions.
</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">trait </span>EncodeMR<M: Mem> {
<span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> {
<span class="prelude-val">None
</span>}
<span class="kw">fn </span>rex<T: Reg>(op1: <span class="kw-2">&</span>M, op2: T) -> <span class="prelude-ty">Option</span><u8> {
<span class="kw">if </span>M::is_64() || op2.is_ext() || op1.base().is_ext() || op1.index().is_ext() {
<span class="prelude-val">Some</span>(rex(
M::is_64(),
op2.idx(),
op1.index().idx(),
op1.base().idx(),
))
} <span class="kw">else </span>{
<span class="prelude-val">None
</span>}
}
}
<span class="kw">impl </span>EncodeMR<Mem8> <span class="kw">for </span>Asm {}
<span class="kw">impl </span>EncodeMR<Mem16> <span class="kw">for </span>Asm {
<span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> {
<span class="prelude-val">Some</span>(<span class="number">0x66</span>)
}
}
<span class="kw">impl </span>EncodeMR<Mem32> <span class="kw">for </span>Asm {}
<span class="kw">impl </span>EncodeMR<Mem64> <span class="kw">for </span>Asm {}
<span class="doccomment">/// Encode helper for memory perand instructions.
</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">trait </span>EncodeM<M: Mem> {
<span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> {
<span class="prelude-val">None
</span>}
<span class="kw">fn </span>rex(op1: <span class="kw-2">&</span>M) -> <span class="prelude-ty">Option</span><u8> {
<span class="kw">if </span>M::is_64() || op1.base().is_ext() || op1.index().is_ext() {
<span class="prelude-val">Some</span>(rex(M::is_64(), <span class="number">0</span>, op1.index().idx(), op1.base().idx()))
} <span class="kw">else </span>{
<span class="prelude-val">None
</span>}
}
}
<span class="kw">impl </span>EncodeM<Mem8> <span class="kw">for </span>Asm {}
<span class="kw">impl </span>EncodeM<Mem16> <span class="kw">for </span>Asm {
<span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> {
<span class="prelude-val">Some</span>(<span class="number">0x66</span>)
}
}
<span class="kw">impl </span>EncodeM<Mem32> <span class="kw">for </span>Asm {}
<span class="kw">impl </span>EncodeM<Mem64> <span class="kw">for </span>Asm {}
</code></pre></div></section></main></body></html>
