diff options
Diffstat (limited to 'src/reg.rs')
| -rw-r--r-- | src/reg.rs | 31 |
1 files changed, 21 insertions, 10 deletions
@@ -1,3 +1,5 @@ +//! Definition of registers which are used as input operands for various instructions. + /// Trait to interact with register operands. pub(crate) trait Reg { /// Get the raw x64 register code. @@ -35,9 +37,9 @@ pub(crate) trait Reg { } } -macro_rules! impl_reg { - (ENUM_ONLY, $name:ident, { $($reg:ident),+ $(,)? }) => { - /// General purpose register operands. +macro_rules! enum_reg { + (#[$doc:meta] $name:ident, { $($reg:ident),+ $(,)? }) => { + #[$doc] #[allow(non_camel_case_types)] #[derive(Copy, Clone)] #[repr(u8)] @@ -53,9 +55,11 @@ macro_rules! impl_reg { } } }; +} - ($name:ident, $rexw:expr, { $($reg:ident),+ $(,)? }) => { - impl_reg!(ENUM_ONLY, $name, { $( $reg, )+ }); +macro_rules! impl_reg { + (#[$doc:meta] $name:ident, $rexw:expr, { $($reg:ident),+ $(,)? }) => { + enum_reg!(#[$doc] $name, { $( $reg, )+ }); impl Reg for $name { /// Get the raw x64 register code. @@ -71,11 +75,18 @@ macro_rules! impl_reg { } } -impl_reg!(Reg64, true, { rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15 }); -impl_reg!(Reg32, false, { eax, ecx, edx, ebx, esp, ebp, esi, edi, r8d, r9d, r10d, r11d, r12d, r13d, r14d, r15d }); -impl_reg!(Reg16, false, { ax, cx, dx, bx, sp, bp, si, di, r8w, r9w, r10w, r11w, r12w, r13w, r14w, r15w }); -impl_reg!(ENUM_ONLY, - Reg8, { al, cl, dl, bl, spl, bpl, sil, dil, r8l, r9l, r10l, r11l, r12l, r13l, r14l, r15l, +impl_reg!( + /// Definition of 64 bit registers. + Reg64, true, { rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15 }); +impl_reg!( + /// Definition of 32 bit registers. + Reg32, false, { eax, ecx, edx, ebx, esp, ebp, esi, edi, r8d, r9d, r10d, r11d, r12d, r13d, r14d, r15d }); +impl_reg!( + /// Definition of 16 bit registers. + Reg16, false, { ax, cx, dx, bx, sp, bp, si, di, r8w, r9w, r10w, r11w, r12w, r13w, r14w, r15w }); +enum_reg!( + /// Definition of 8 bit registers. + Reg8, { al, cl, dl, bl, spl, bpl, sil, dil, r8l, r9l, r10l, r11l, r12l, r13l, r14l, r15l, ah, ch, dh, bh }); impl Reg for Reg8 { |