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-rw-r--r-- | src/add/add.rs.html | 77 | ||||
-rw-r--r-- | src/fib/fib.rs.html | 157 | ||||
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-rw-r--r-- | src/juicebox_asm/insn/add.rs.html | 26 | ||||
-rw-r--r-- | src/juicebox_asm/insn/call.rs.html | 2 | ||||
-rw-r--r-- | src/juicebox_asm/insn/cmp.rs.html | 15 | ||||
-rw-r--r-- | src/juicebox_asm/insn/dec.rs.html | 2 | ||||
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-rw-r--r-- | src/juicebox_asm/insn/mov.rs.html | 18 | ||||
-rw-r--r-- | src/juicebox_asm/insn/nop.rs.html | 2 | ||||
-rw-r--r-- | src/juicebox_asm/insn/ret.rs.html | 2 | ||||
-rw-r--r-- | src/juicebox_asm/insn/test.rs.html | 14 | ||||
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-rw-r--r-- | src/tiny_vm/tiny_vm.rs.html | 1395 |
21 files changed, 1923 insertions, 39 deletions
diff --git a/src/add/add.rs.html b/src/add/add.rs.html new file mode 100644 index 0000000..112d0f1 --- /dev/null +++ b/src/add/add.rs.html @@ -0,0 +1,77 @@ +<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Source of the Rust file `examples/add.rs`."><title>add.rs - source</title><link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/SourceSerif4-Regular-46f98efaafac5295.ttf.woff2"><link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/FiraSans-Regular-018c141bf0843ffd.woff2"><link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/FiraSans-Medium-8f9a781e4970d388.woff2"><link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2"><link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/SourceSerif4-Bold-a2c9cd1067f8b328.ttf.woff2"><link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2"><link rel="stylesheet" href="../../static.files/normalize-76eba96aa4d2e634.css"><link rel="stylesheet" href="../../static.files/rustdoc-fa3bb1812debf86c.css"><meta name="rustdoc-vars" data-root-path="../../" data-static-root-path="../../static.files/" data-current-crate="add" data-themes="" data-resource-suffix="" data-rustdoc-version="1.74.0 (79e9716c9 2023-11-13)" data-channel="1.74.0" data-search-js="search-8be46b629f5f14a8.js" data-settings-js="settings-74424d7eec62a23e.js" ><script src="../../static.files/storage-fec3eaa3851e447d.js"></script><script defer src="../../static.files/src-script-3280b574d94e47b4.js"></script><script defer src="../../src-files.js"></script><script defer src="../../static.files/main-c5bd66d33317d69f.js"></script><noscript><link rel="stylesheet" href="../../static.files/noscript-5d8b3c7633ad77ba.css"></noscript><link rel="alternate icon" type="image/png" href="../../static.files/favicon-16x16-8b506e7a72182f1c.png"><link rel="alternate icon" type="image/png" href="../../static.files/favicon-32x32-422f7d1d52889060.png"><link rel="icon" type="image/svg+xml" href="../../static.files/favicon-2c020d218678b618.svg"></head><body class="rustdoc src"><!--[if lte IE 11]><div class="warning">This old browser is unsupported and will most likely display funky things.</div><![endif]--><nav class="sidebar"></nav><main><nav class="sub"><a class="sub-logo-container" href="../../add/index.html"><img class="rust-logo" src="../../static.files/rust-logo-151179464ae7ed46.svg" alt="logo"></a><form class="search-form"><span></span><input class="search-input" name="search" aria-label="Run search in the documentation" autocomplete="off" spellcheck="false" placeholder="Click or press ‘S’ to search, ‘?’ for more options…" type="search"><div id="help-button" title="help" tabindex="-1"><a href="../../help.html">?</a></div><div id="settings-menu" tabindex="-1"><a href="../../settings.html" title="settings"><img width="22" height="22" alt="Change settings" src="../../static.files/wheel-7b819b6101059cd0.svg"></a></div></form></nav><section id="main-content" class="content"><div class="example-wrap"><div data-nosnippet><pre class="src-line-numbers"><a href="#1" id="1">1</a> +<a href="#2" id="2">2</a> +<a href="#3" id="3">3</a> +<a href="#4" id="4">4</a> +<a href="#5" id="5">5</a> +<a href="#6" id="6">6</a> +<a href="#7" id="7">7</a> +<a href="#8" id="8">8</a> +<a href="#9" id="9">9</a> +<a href="#10" id="10">10</a> +<a href="#11" id="11">11</a> +<a href="#12" id="12">12</a> +<a href="#13" id="13">13</a> +<a href="#14" id="14">14</a> +<a href="#15" id="15">15</a> +<a href="#16" id="16">16</a> +<a href="#17" id="17">17</a> +<a href="#18" id="18">18</a> +<a href="#19" id="19">19</a> +<a href="#20" id="20">20</a> +<a href="#21" id="21">21</a> +<a href="#22" id="22">22</a> +<a href="#23" id="23">23</a> +<a href="#24" id="24">24</a> +<a href="#25" id="25">25</a> +<a href="#26" id="26">26</a> +<a href="#27" id="27">27</a> +<a href="#28" id="28">28</a> +<a href="#29" id="29">29</a> +<a href="#30" id="30">30</a> +<a href="#31" id="31">31</a> +<a href="#32" id="32">32</a> +<a href="#33" id="33">33</a> +<a href="#34" id="34">34</a> +<a href="#35" id="35">35</a> +<a href="#36" id="36">36</a> +<a href="#37" id="37">37</a> +<a href="#38" id="38">38</a> +</pre></div><pre class="rust"><code><span class="doccomment">//! Add example. +//! +//! Jit compile a function at runtime (generate native host code) which calls a function defined in +//! the example based on the SystemV abi to demonstrate the [`juicebox_asm`] crate. + +</span><span class="attr">#[cfg(not(any(target_arch = <span class="string">"x86_64"</span>, target_os = <span class="string">"linux"</span>)))] +</span><span class="macro">compile_error!</span>(<span class="string">"Only supported on x86_64 with SystemV abi"</span>); + +<span class="kw">use </span>juicebox_asm::prelude::<span class="kw-2">*</span>; +<span class="kw">use </span>juicebox_asm::Runtime; +<span class="kw">use </span>Reg64::<span class="kw-2">*</span>; + +<span class="kw">extern </span><span class="string">"C" </span><span class="kw">fn </span>add(a: u32, b: u32) -> u32 { + a + b +} + +<span class="kw">fn </span>main() { + <span class="kw">let </span><span class="kw-2">mut </span>asm = Asm::new(); + + <span class="comment">// SystemV abi: + // rdi -> first argument + // rsi -> second argument + // rax -> return value + // + </span>asm.mov(rsi, Imm64::from(<span class="number">42</span>)); + asm.mov(rax, Imm64::from(add <span class="kw">as </span>u64)); + asm.call(rax); + asm.ret(); + + <span class="kw">let </span>code = asm.into_code(); + std::fs::write(<span class="string">"jit.asm"</span>, <span class="kw-2">&</span>code).unwrap(); + + <span class="kw">let </span><span class="kw-2">mut </span>rt = Runtime::new(); + <span class="kw">let </span>add42 = <span class="kw">unsafe </span>{ rt.add_code::<<span class="kw">extern </span><span class="string">"C" </span><span class="kw">fn</span>(u32) -> u32>(code) }; + + <span class="kw">let </span>res = add42(<span class="number">5</span>); + <span class="macro">assert_eq!</span>(res, <span class="number">47</span>); +} +</code></pre></div></section></main></body></html>
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id="18">18</a> +<a href="#19" id="19">19</a> +<a href="#20" id="20">20</a> +<a href="#21" id="21">21</a> +<a href="#22" id="22">22</a> +<a href="#23" id="23">23</a> +<a href="#24" id="24">24</a> +<a href="#25" id="25">25</a> +<a href="#26" id="26">26</a> +<a href="#27" id="27">27</a> +<a href="#28" id="28">28</a> +<a href="#29" id="29">29</a> +<a href="#30" id="30">30</a> +<a href="#31" id="31">31</a> +<a href="#32" id="32">32</a> +<a href="#33" id="33">33</a> +<a href="#34" id="34">34</a> +<a href="#35" id="35">35</a> +<a href="#36" id="36">36</a> +<a href="#37" id="37">37</a> +<a href="#38" id="38">38</a> +<a href="#39" id="39">39</a> +<a href="#40" id="40">40</a> +<a href="#41" id="41">41</a> +<a href="#42" id="42">42</a> +<a href="#43" id="43">43</a> +<a href="#44" id="44">44</a> +<a href="#45" id="45">45</a> +<a href="#46" id="46">46</a> +<a href="#47" id="47">47</a> +<a href="#48" id="48">48</a> +<a href="#49" id="49">49</a> +<a href="#50" id="50">50</a> +<a href="#51" id="51">51</a> +<a href="#52" id="52">52</a> +<a href="#53" id="53">53</a> +<a href="#54" id="54">54</a> +<a href="#55" id="55">55</a> +<a href="#56" id="56">56</a> +<a href="#57" id="57">57</a> +<a href="#58" id="58">58</a> +<a href="#59" id="59">59</a> +<a href="#60" id="60">60</a> +<a href="#61" id="61">61</a> +<a href="#62" id="62">62</a> +<a href="#63" id="63">63</a> +<a href="#64" id="64">64</a> +<a href="#65" id="65">65</a> +<a href="#66" id="66">66</a> +<a href="#67" id="67">67</a> +<a href="#68" id="68">68</a> +<a href="#69" id="69">69</a> +<a href="#70" id="70">70</a> +<a href="#71" id="71">71</a> +<a href="#72" id="72">72</a> +<a href="#73" id="73">73</a> +<a href="#74" id="74">74</a> +<a href="#75" id="75">75</a> +<a href="#76" id="76">76</a> +<a href="#77" id="77">77</a> +<a href="#78" id="78">78</a> +</pre></div><pre class="rust"><code><span class="doccomment">//! Fibonacci example. +//! +//! Jit compile a function at runtime (generate native host code) to compute the fibonacci sequence +//! to demonstrate the [`juicebox_asm`] crate. + +</span><span class="kw">use </span>juicebox_asm::prelude::<span class="kw-2">*</span>; +<span class="kw">use </span>juicebox_asm::Runtime; + +<span class="kw">const fn </span>fib_rs(n: u64) -> u64 { + <span class="kw">match </span>n { + <span class="number">0 </span>=> <span class="number">0</span>, + <span class="number">1 </span>=> <span class="number">1</span>, + <span class="kw">_ </span>=> fib_rs(n - <span class="number">2</span>) + fib_rs(n - <span class="number">1</span>), + } +} + +<span class="kw">fn </span>main() { + <span class="kw">let </span><span class="kw-2">mut </span>asm = Asm::new(); + + <span class="kw">let </span><span class="kw-2">mut </span>lp = Label::new(); + <span class="kw">let </span><span class="kw-2">mut </span>end = Label::new(); + + <span class="comment">// Reference implementation: + // + // int fib(int n) { + // int tmp = 0; + // int prv = 1; + // int sum = 0; + // loop: + // if (n == 0) goto end; + // tmp = sum; + // sum += prv; + // prv = tmp; + // --n; + // goto loop; + // end: + // return sum; + // } + + // SystemV abi: + // rdi -> first argument + // rax -> return value + </span><span class="kw">let </span>n = Reg64::rdi; + <span class="kw">let </span>sum = Reg64::rax; + + <span class="kw">let </span>tmp = Reg64::rcx; + <span class="kw">let </span>prv = Reg64::rbx; + + asm.mov(tmp, Imm64::from(<span class="number">0</span>)); + asm.mov(prv, Imm64::from(<span class="number">1</span>)); + asm.mov(sum, Imm64::from(<span class="number">0</span>)); + + asm.bind(<span class="kw-2">&mut </span>lp); + asm.test(n, n); + asm.jz(<span class="kw-2">&mut </span>end); + asm.mov(tmp, sum); + asm.add(sum, prv); + asm.mov(prv, tmp); + asm.dec(n); + asm.jmp(<span class="kw-2">&mut </span>lp); + asm.bind(<span class="kw-2">&mut </span>end); + asm.ret(); + + <span class="comment">// Write out JIT code for visualization. + // Disassemble for example with `ndisasm -b 64 jit.asm`. + </span><span class="kw">let </span>code = asm.into_code(); + std::fs::write(<span class="string">"jit.asm"</span>, <span class="kw-2">&</span>code).unwrap(); + + <span class="comment">// Move code into executable page and get function pointer to it. + </span><span class="kw">let </span><span class="kw-2">mut </span>rt = Runtime::new(); + <span class="kw">let </span>fib = <span class="kw">unsafe </span>{ rt.add_code::<<span class="kw">extern </span><span class="string">"C" </span><span class="kw">fn</span>(u64) -> u64>(code) }; + + <span class="kw">for </span>n <span class="kw">in </span><span class="number">0</span>..<span class="number">15 </span>{ + <span class="kw">let </span>fib_jit = fib(n); + <span class="macro">println!</span>(<span class="string">"fib({}) = {}"</span>, n, fib_jit); + <span class="macro">assert_eq!</span>(fib_jit, fib_rs(n)); + } +} +</code></pre></div></section></main></body></html>
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Trait definitions of various instructions. </span><span class="kw">mod </span>add; <span class="kw">mod </span>call; +<span class="kw">mod </span>cmp; <span class="kw">mod </span>dec; <span class="kw">mod </span>jmp; <span class="kw">mod </span>jnz; @@ -76,6 +83,11 @@ </span><span class="kw">fn </span>call(<span class="kw-2">&mut </span><span class="self">self</span>, op1: T); } +<span class="kw">pub trait </span>Cmp<T, U> { + <span class="doccomment">/// Emit a compare call instruction. + </span><span class="kw">fn </span>cmp(<span class="kw-2">&mut </span><span class="self">self</span>, op1: T, op2: U); +} + <span class="kw">pub trait </span>Dec<T> { <span class="doccomment">/// Emit a decrement instruction. </span><span class="kw">fn </span>dec(<span class="kw-2">&mut </span><span class="self">self</span>, op1: T); diff --git a/src/juicebox_asm/insn/add.rs.html b/src/juicebox_asm/insn/add.rs.html index 0a24951..d7f968a 100644 --- a/src/juicebox_asm/insn/add.rs.html +++ b/src/juicebox_asm/insn/add.rs.html @@ -1,4 +1,4 @@ -<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Source of the Rust file `src/insn/add.rs`."><title>add.rs - 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id="409">409</a> <a href="#410" id="410">410</a> +<a href="#411" id="411">411</a> +<a href="#412" id="412">412</a> +<a href="#413" id="413">413</a> +<a href="#414" id="414">414</a> +<a href="#415" id="415">415</a> +<a href="#416" id="416">416</a> +<a href="#417" id="417">417</a> +<a href="#418" id="418">418</a> +<a href="#419" id="419">419</a> +<a href="#420" id="420">420</a> +<a href="#421" id="421">421</a> +<a href="#422" id="422">422</a> +<a href="#423" id="423">423</a> +<a href="#424" id="424">424</a> +<a href="#425" id="425">425</a> +<a href="#426" id="426">426</a> +<a href="#427" id="427">427</a> +<a href="#428" id="428">428</a> +<a href="#429" id="429">429</a> +<a href="#430" id="430">430</a> +<a href="#431" id="431">431</a> +<a href="#432" id="432">432</a> +<a href="#433" id="433">433</a> +<a href="#434" id="434">434</a> +<a href="#435" id="435">435</a> +<a href="#436" id="436">436</a> +<a href="#437" id="437">437</a> +<a href="#438" id="438">438</a> +<a href="#439" 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id="469">469</a> </pre></div><pre class="rust"><code><span class="doccomment">//! A simple `x64` jit assembler with a minimal runtime to execute emitted code for fun. //! //! The following is an fibonacci example implementation. @@ -471,8 +530,8 @@ //! asm.ret(); //! //! // Move code into executable page and get function pointer to it. -//! let rt = Runtime::new(&asm.into_code()); -//! let fib = unsafe { rt.as_fn::<extern "C" fn(u64) -> u64>() }; +//! let mut rt = Runtime::new(); +//! let fib = unsafe { rt.add_code::<extern "C" fn(u64) -> u64>(&asm.into_code()) }; //! //! for n in 0..15 { //! let fib_jit = fib(n); @@ -683,6 +742,42 @@ <span class="self">self</span>.emit(<span class="kw-2">&</span>[opc, modrm]); } + <span class="doccomment">/// Encode a memory-immediate instruction. + </span><span class="kw">fn </span>encode_mi<T: Imm>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, opc_ext: u8, op1: MemOp, op2: T) + <span class="kw">where + </span><span class="self">Self</span>: EncodeMI<T>, + { + <span class="comment">// MI operand encoding. + // op1 -> modrm.rm + // op2 -> imm + </span><span class="kw">let </span>mode = <span class="kw">match </span>op1 { + MemOp::Indirect(..) => { + <span class="macro">assert!</span>(!op1.base().need_sib() && !op1.base().is_pc_rel()); + <span class="number">0b00 + </span>} + MemOp::IndirectDisp(..) => { + <span class="macro">assert!</span>(!op1.base().need_sib()); + <span class="number">0b10 + </span>} + }; + + <span class="kw">let </span>modrm = modrm( + mode, <span class="comment">/* mode */ + </span>opc_ext, <span class="comment">/* reg */ + </span>op1.base().idx(), <span class="comment">/* rm */ + </span>); + + <span class="kw">let </span>prefix = <<span class="self">Self </span><span class="kw">as </span>EncodeMI<T>>::legacy_prefix(); + <span class="kw">let </span>rex = <<span class="self">Self </span><span class="kw">as </span>EncodeMI<T>>::rex(<span class="kw-2">&</span>op1); + + <span class="self">self</span>.emit_optional(<span class="kw-2">&</span>[prefix, rex]); + <span class="self">self</span>.emit(<span class="kw-2">&</span>[opc, modrm]); + <span class="kw">if let </span>MemOp::IndirectDisp(<span class="kw">_</span>, disp) = op1 { + <span class="self">self</span>.emit(<span class="kw-2">&</span>disp.to_ne_bytes()); + } + <span class="self">self</span>.emit(op2.bytes()); + } + <span class="doccomment">/// Encode a memory-register instruction. </span><span class="kw">fn </span>encode_mr<T: Reg>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, op1: MemOp, op2: T) <span class="kw">where @@ -818,4 +913,27 @@ } <span class="kw">impl </span>EncodeMR<Reg32> <span class="kw">for </span>Asm {} <span class="kw">impl </span>EncodeMR<Reg64> <span class="kw">for </span>Asm {} + +<span class="doccomment">/// Encode helper for memory-immediate instructions. +</span><span class="kw">trait </span>EncodeMI<T: Imm> { + <span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> { + <span class="prelude-val">None + </span>} + + <span class="kw">fn </span>rex(op1: <span class="kw-2">&</span>MemOp) -> <span class="prelude-ty">Option</span><u8> { + <span class="kw">if </span>op1.base().is_ext() { + <span class="prelude-val">Some</span>(rex(<span class="bool-val">false</span>, <span class="number">0</span>, <span class="number">0</span>, op1.base().idx())) + } <span class="kw">else </span>{ + <span class="prelude-val">None + </span>} + } +} + +<span class="kw">impl </span>EncodeMI<Imm8> <span class="kw">for </span>Asm {} +<span class="kw">impl </span>EncodeMI<Imm16> <span class="kw">for </span>Asm { + <span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> { + <span class="prelude-val">Some</span>(<span class="number">0x66</span>) + } +} +<span class="kw">impl </span>EncodeMI<Imm32> <span class="kw">for </span>Asm {} </code></pre></div></section></main></body></html>
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A simple runtime which can be used to execute emitted instructions. -</span><span class="kw">use </span>core::ffi::c_void; +</span><span class="kw">use </span>core::slice; <span class="kw">use </span>nix::sys::mman::{mmap, mprotect, munmap, MapFlags, ProtFlags}; <span class="doccomment">/// A simple `mmap`ed runtime with executable pages. </span><span class="kw">pub struct </span>Runtime { - buf: <span class="kw-2">*mut </span>c_void, + buf: <span class="kw-2">*mut </span>u8, len: usize, + idx: usize, } <span class="kw">impl </span>Runtime { <span class="doccomment">/// Create a new [Runtime]. - </span><span class="kw">pub fn </span>new(code: <span class="kw">impl </span>AsRef<[u8]>) -> Runtime { + </span><span class="kw">pub fn </span>new() -> Runtime { <span class="comment">// Allocate a single page. </span><span class="kw">let </span>len = core::num::NonZeroUsize::new(<span class="number">4096</span>).unwrap(); <span class="kw">let </span>buf = <span class="kw">unsafe </span>{ mmap( <span class="prelude-val">None</span>, len, - ProtFlags::PROT_WRITE, + ProtFlags::PROT_WRITE | ProtFlags::PROT_READ | ProtFlags::PROT_EXEC, MapFlags::MAP_PRIVATE | MapFlags::MAP_ANONYMOUS, <span class="number">0</span>, <span class="comment">/* fd */ </span><span class="number">0</span>, <span class="comment">/* off */ </span>) - .unwrap() + .unwrap() <span class="kw">as </span><span class="kw-2">*mut </span>u8 }; - { - <span class="comment">// Copy over code. - </span><span class="kw">let </span>code = code.as_ref(); - <span class="macro">assert!</span>(code.len() < len.get()); - <span class="kw">unsafe </span>{ std::ptr::copy_nonoverlapping(code.as_ptr(), buf.cast(), len.get()) }; - } - <span class="kw">unsafe </span>{ - <span class="comment">// Remove write permissions from code buffer and allow to read-execute from it. - </span>mprotect(buf, len.get(), ProtFlags::PROT_READ | ProtFlags::PROT_EXEC) - .expect(<span class="string">"Failed to RX mprotect Runtime code buffer"</span>); - } Runtime { buf, len: len.get(), + idx: <span class="number">0</span>, + } + } + + <span class="doccomment">/// Write protect the underlying code page(s). + </span><span class="kw">pub fn </span>protect(<span class="kw-2">&mut </span><span class="self">self</span>) { + <span class="kw">unsafe </span>{ + <span class="comment">// Remove write permissions from code buffer and allow to read-execute from it. + </span>mprotect( + <span class="self">self</span>.buf.cast(), + <span class="self">self</span>.len, + ProtFlags::PROT_READ | ProtFlags::PROT_EXEC, + ) + .expect(<span class="string">"Failed to RX mprotect Runtime code buffer"</span>); } } + <span class="doccomment">/// Add block of code to the runtime and get function pointer back. + </span><span class="kw">pub unsafe fn </span>add_code<F>(<span class="kw-2">&mut </span><span class="self">self</span>, code: <span class="kw">impl </span>AsRef<[u8]>) -> F { + <span class="comment">// Get pointer to start of next free byte. + </span><span class="macro">assert!</span>(<span class="self">self</span>.idx < <span class="self">self</span>.len); + <span class="kw">let </span>fn_start = <span class="self">self</span>.buf.add(<span class="self">self</span>.idx); + + <span class="comment">// Copy over code. + </span><span class="kw">let </span>code = code.as_ref(); + <span class="macro">assert!</span>(code.len() < (<span class="self">self</span>.len - <span class="self">self</span>.idx)); + <span class="kw">unsafe </span>{ std::ptr::copy_nonoverlapping(code.as_ptr(), fn_start, code.len()) }; + + <span class="comment">// Increment index to next free byte. + </span><span class="self">self</span>.idx += code.len(); + + <span class="comment">// Return function to newly added code. + </span><span class="self">Self</span>::as_fn::<F>(fn_start) + } + <span class="doccomment">/// Reinterpret the block of code as `F`. </span><span class="attr">#[inline] - </span><span class="kw">pub unsafe fn </span>as_fn<F>(<span class="kw-2">&</span><span class="self">self</span>) -> F { - <span class="kw">unsafe </span>{ std::mem::transmute_copy(<span class="kw-2">&</span><span class="self">self</span>.buf) } + </span><span class="kw">unsafe fn </span>as_fn<F>(fn_start: <span class="kw-2">*mut </span>u8) -> F { + <span class="kw">unsafe </span>{ std::mem::transmute_copy(<span class="kw-2">&</span>fn_start) } + } + + <span class="doccomment">/// Dump the currently added code to a file called `jit.asm`. The disassembly can be inspected + /// as `ndisasm -b 64 jit.asm`. + </span><span class="kw">pub fn </span>dump(<span class="kw-2">&</span><span class="self">self</span>) { + <span class="kw">let </span>code = <span class="kw">unsafe </span>{ slice::from_raw_parts(<span class="self">self</span>.buf, <span class="self">self</span>.idx) }; + std::fs::write(<span class="string">"jit.asm"</span>, code).unwrap(); } } <span class="kw">impl </span>Drop <span class="kw">for </span>Runtime { <span class="kw">fn </span>drop(<span class="kw-2">&mut </span><span class="self">self</span>) { <span class="kw">unsafe </span>{ - munmap(<span class="self">self</span>.buf, <span class="self">self</span>.len).expect(<span class="string">"Failed to munmap Runtime"</span>); + munmap(<span class="self">self</span>.buf.cast(), <span class="self">self</span>.len).expect(<span class="string">"Failed to munmap Runtime"</span>); } } } diff --git a/src/tiny_vm/tiny_vm.rs.html b/src/tiny_vm/tiny_vm.rs.html new file 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TinyVm example. +//! +//! This example introduces as simple 16 bit virtual machine the [`TinyVm`]. The VM consits of +//! three registers defined in [`TinyReg`], a separate _data_ and _insutrction_ memory and a small +//! set of instructions [`TinyInsn`], sufficient to implement a guest program to compute the +//! fiibonacci sequence. +//! +//! The `TinyVm` implements a simple _just-in-time (JIT)_ compiler to demonstrate the +//! [`juicebox_asm`] crate. Additionally, it implements a reference _interpreter_. +//! +//! ``` +//! fn main() { +//! let mut prog = Vec::new(); +//! prog.push(TinyInsn::LoadImm(TinyReg::A, 100)); +//! prog.push(TinyInsn::Add(TinyReg::B, TinyReg::A)); +//! prog.push(TinyInsn::Addi(TinyReg::C, 100)); +//! prog.push(TinyInsn::Halt); +//! +//! let mut vm = TinyVm::new(prog); +//! vm.interp(); +//! +//! assert_eq!(100, vm.read_reg(TinyReg::A)); +//! assert_eq!(100, vm.read_reg(TinyReg::B)); +//! assert_eq!(100, vm.read_reg(TinyReg::C)); +//! assert_eq!(4, vm.icnt); +//! assert_eq!(4, vm.pc); +//! +//! vm.pc = 0; +//! vm.jit(); +//! +//! assert_eq!(100, vm.read_reg(TinyReg::A)); +//! assert_eq!(200, vm.read_reg(TinyReg::B)); +//! assert_eq!(200, vm.read_reg(TinyReg::C)); +//! assert_eq!(8, vm.icnt); +//! assert_eq!(4, vm.pc); +//! } +//! ``` + +</span><span class="attr">#[cfg(not(any(target_arch = <span class="string">"x86_64"</span>, target_os = <span class="string">"linux"</span>)))] +</span><span class="macro">compile_error!</span>(<span class="string">"Only supported on x86_64 with SystemV abi"</span>); + +<span class="kw">use </span>juicebox_asm::prelude::<span class="kw-2">*</span>; +<span class="kw">use </span>juicebox_asm::Runtime; + +<span class="doccomment">/// A guest physical address. +</span><span class="kw">pub struct </span>PhysAddr(<span class="kw">pub </span>u16); + +<span class="kw">impl </span>Into<usize> <span class="kw">for </span>PhysAddr { + <span class="kw">fn </span>into(<span class="self">self</span>) -> usize { + <span class="self">self</span>.<span class="number">0 </span><span class="kw">as </span>usize + } +} + +<span class="doccomment">/// The registers for the [`TinyVm`]. +</span><span class="attr">#[derive(Debug, PartialEq, Clone, Copy)] +</span><span class="kw">pub enum </span>TinyReg { + A, + B, + C, +} + +<span class="kw">impl </span>TinyReg { + <span class="attr">#[inline] + </span><span class="kw">fn </span>idx(<span class="kw-2">&</span><span class="self">self</span>) -> usize { + <span class="kw-2">*</span><span class="self">self </span><span class="kw">as </span>usize + } +} + +<span class="doccomment">/// The instructions for the [`TinyVm`]. +</span><span class="attr">#[derive(Debug, PartialEq, Clone, Copy)] +</span><span class="kw">pub enum </span>TinyInsn { + <span class="doccomment">/// Halt the VM. + </span>Halt, + <span class="doccomment">/// Load the immediate value into the register `reg = imm`. + </span>LoadImm(TinyReg, u16), + <span class="doccomment">/// Load a value from the memory (absolute addressing) into the register `reg = mem[imm]`. + </span>Load(TinyReg, u16), + <span class="doccomment">/// Store a value from the register into the memory (absolute addressing) `mem[imm] = reg`. + </span>Store(TinyReg, u16), + <span class="doccomment">/// Add the register to the register `reg1 += reg2`. + </span>Add(TinyReg, TinyReg), + <span class="doccomment">/// Add the immediate to the register `reg += imm`. + </span>Addi(TinyReg, i16), + <span class="doccomment">/// Jump unconditional (absolute addressing) `pc = disp`. + </span>Branch(usize), + <span class="doccomment">/// Jump if the register is zero (absolute addressing) `pc = (reg == 0) ? disp : pc++`. + </span>BranchZero(TinyReg, usize), +} + +<span class="doccomment">/// Value returned from a [`JitFn`]. +</span><span class="attr">#[repr(C)] +</span><span class="kw">struct </span>JitRet(u64, u64); + +<span class="doccomment">/// Function signature defining the simple JIT ABI used in this example. +/// A `JitFn` represents the entry point to a jit compiled _basic block_ of the guest software. +/// +/// ```text +/// JIT entry: +/// arg0: pointer to guest registers +/// arg1: pointer to guest data memory +/// +/// JIT exit: +/// JitRet(0, N): Halt instruction, executed N instructions. +/// JitRet(N, R): N!=0 +/// End of basic block, executed N instructions, +/// must re-enter at `pc = R`. +/// ``` +</span><span class="kw">type </span>JitFn = <span class="kw">extern </span><span class="string">"C" </span><span class="kw">fn</span>(<span class="kw-2">*mut </span>u16, <span class="kw-2">*mut </span>u8) -> JitRet; + +<span class="doccomment">/// The `TinyVm` virtual machine state. +</span><span class="kw">pub struct </span>TinyVm { + <span class="doccomment">/// Data memory, covering full 16 bit guest address space. + /// + /// For simplicity add additional trailing 1 byte to support an unaligned access to 0xffff + /// without any special handling. + </span>dmem: [u8; <span class="number">0x1_0000 </span>+ <span class="number">1</span>], + <span class="doccomment">/// Instruction memory. + </span>imem: Vec<TinyInsn>, + <span class="doccomment">/// VM registers. + </span>regs: [u16; <span class="number">3</span>], + <span class="doccomment">/// VM program counter. + </span>pc: usize, + <span class="doccomment">/// VM executed instruction counter (perf counter). + </span>icnt: usize, + + <span class="comment">// -- JIT state. + </span><span class="doccomment">/// Mapping of guest PCs to jitted host code (`JitFn`). This mapping is filled when guest + /// _basic blocks_ are jitted. + </span>jit_cache: Vec<<span class="prelude-ty">Option</span><JitFn>>, + <span class="doccomment">/// JIT runtime maintaining the host pages containing the jitted guest code. + </span>rt: Runtime, +} + +<span class="kw">impl </span>TinyVm { + <span class="doccomment">/// Create a new [`TinyVm`] and initialize the instruction memory from `code`. + </span><span class="kw">pub fn </span>new(code: Vec<TinyInsn>) -> <span class="self">Self </span>{ + <span class="kw">let </span><span class="kw-2">mut </span>jit_cache = Vec::with_capacity(code.len()); + jit_cache.resize(code.len(), <span class="prelude-val">None</span>); + + TinyVm { + dmem: [<span class="number">0</span>; <span class="number">0x1_0000 </span>+ <span class="number">1</span>], + imem: code, + regs: [<span class="number">0</span>; <span class="number">3</span>], + pc: <span class="number">0</span>, + icnt: <span class="number">0</span>, + <span class="comment">// -- JIT state. + </span>jit_cache, + rt: Runtime::new(), + } + } + + <span class="doccomment">/// Read guest register. + </span><span class="attr">#[inline] + </span><span class="kw">pub fn </span>read_reg(<span class="kw-2">&</span><span class="self">self</span>, reg: TinyReg) -> u16 { + <span class="self">self</span>.regs[reg.idx()] + } + + <span class="doccomment">/// Write guest register. + </span><span class="attr">#[inline] + </span><span class="kw">pub fn </span>write_reg(<span class="kw-2">&mut </span><span class="self">self</span>, reg: TinyReg, val: u16) { + <span class="self">self</span>.regs[reg.idx()] = val; + } + + <span class="doccomment">/// Read guest data memory. + </span><span class="attr">#[inline] + </span><span class="kw">pub fn </span>read_mem(<span class="kw-2">&</span><span class="self">self</span>, paddr: PhysAddr) -> u16 { + <span class="comment">// dmem covers whole 16 bit address space + 1 byte for unaligned access at 0xffff. + </span><span class="kw">let </span>bytes = <span class="self">self</span>.dmem[paddr.into()..][..<span class="number">2</span>].try_into().unwrap(); + u16::from_le_bytes(bytes) + } + + <span class="doccomment">/// Write guest data memory. + </span><span class="attr">#[inline] + </span><span class="kw">pub fn </span>write_mem(<span class="kw-2">&mut </span><span class="self">self</span>, paddr: PhysAddr, val: u16) { + <span class="kw">let </span>bytes = val.to_le_bytes(); + <span class="self">self</span>.dmem[paddr.into()..][..<span class="number">2</span>].copy_from_slice(<span class="kw-2">&</span>bytes); + } + + <span class="doccomment">/// Dump the VM state to stdout. + </span><span class="kw">pub fn </span>dump(<span class="kw-2">&</span><span class="self">self</span>) { + <span class="macro">println!</span>(<span class="string">"-- TinyVm state --"</span>); + <span class="macro">println!</span>(<span class="string">" ICNT: {}"</span>, <span class="self">self</span>.icnt); + <span class="macro">println!</span>(<span class="string">" PC : {:02x}"</span>, <span class="self">self</span>.pc - <span class="number">1</span>); + <span class="macro">println!</span>( + <span class="string">" A:{:04x} B:{:04x} C:{:04x}"</span>, + <span class="self">self</span>.read_reg(TinyReg::A), + <span class="self">self</span>.read_reg(TinyReg::B), + <span class="self">self</span>.read_reg(TinyReg::C), + ); + } + + <span class="doccomment">/// Run in interpreter mode until the next [`TinyInsn::Halt`] instruction is hit. + </span><span class="kw">pub fn </span>interp(<span class="kw-2">&mut </span><span class="self">self</span>) { + <span class="lifetime">'outer</span>: <span class="kw">loop </span>{ + <span class="kw">let </span>insn = <span class="self">self</span>.imem[<span class="self">self</span>.pc]; + <span class="comment">//println!("[0x{:02x}] {:?}", self.pc, insn); + + </span><span class="self">self</span>.pc = <span class="self">self</span>.pc.wrapping_add(<span class="number">1</span>); + <span class="self">self</span>.icnt += <span class="number">1</span>; + + <span class="kw">match </span>insn { + TinyInsn::Halt => { + <span class="kw">break </span><span class="lifetime">'outer</span>; + } + TinyInsn::LoadImm(a, imm) => { + <span class="self">self</span>.write_reg(a, imm); + } + TinyInsn::Load(a, addr) => { + <span class="kw">let </span>val = <span class="self">self</span>.read_mem(PhysAddr(addr)); + <span class="self">self</span>.write_reg(a, val); + } + TinyInsn::Store(a, addr) => { + <span class="kw">let </span>val = <span class="self">self</span>.read_reg(a); + <span class="self">self</span>.write_mem(PhysAddr(addr), val); + } + TinyInsn::Add(a, b) => { + <span class="kw">let </span>res = <span class="self">self</span>.read_reg(a).wrapping_add(<span class="self">self</span>.read_reg(b)); + <span class="self">self</span>.write_reg(a, res); + } + TinyInsn::Addi(a, imm) => { + <span class="kw">let </span>res = <span class="self">self</span>.read_reg(a).wrapping_add(imm <span class="kw">as </span>u16); + <span class="self">self</span>.write_reg(a, res); + } + TinyInsn::Branch(disp) => { + <span class="self">self</span>.pc = disp; + } + TinyInsn::BranchZero(a, disp) => { + <span class="kw">if </span><span class="self">self</span>.read_reg(a) == <span class="number">0 </span>{ + <span class="self">self</span>.pc = disp; + } + } + } + } + } + + <span class="doccomment">/// Run in JIT mode until the next [`TinyInsn::Halt`] instruction is hit. Translate guest + /// _basic blocks_ on demand. + </span><span class="kw">pub fn </span>jit(<span class="kw-2">&mut </span><span class="self">self</span>) { + <span class="lifetime">'outer</span>: <span class="kw">loop </span>{ + <span class="kw">if let </span><span class="prelude-val">Some</span>(bb_fn) = <span class="self">self</span>.jit_cache[<span class="self">self</span>.pc] { + <span class="kw">match </span>bb_fn(<span class="self">self</span>.regs.as_mut_ptr(), <span class="self">self</span>.dmem.as_mut_ptr()) { + JitRet(<span class="number">0</span>, insn) => { + <span class="self">self</span>.pc += insn <span class="kw">as </span>usize; + <span class="self">self</span>.icnt += insn <span class="kw">as </span>usize; + <span class="kw">break </span><span class="lifetime">'outer</span>; + } + JitRet(insn, reenter_pc) => { + <span class="self">self</span>.pc = reenter_pc <span class="kw">as </span>usize; + <span class="self">self</span>.icnt += insn <span class="kw">as </span>usize; + } + } + } <span class="kw">else </span>{ + <span class="kw">let </span>bb_fn = <span class="self">self</span>.translate_next_bb(); + <span class="self">self</span>.jit_cache[<span class="self">self</span>.pc] = <span class="prelude-val">Some</span>(bb_fn); + <span class="comment">//println!("[0x{:02x}] translated bb at {:p}", self.pc, bb_fn); + </span>} + } + } + + <span class="doccomment">/// Translate the bb at the current pc and return a JitFn pointer to it. + </span><span class="kw">fn </span>translate_next_bb(<span class="kw-2">&mut </span><span class="self">self</span>) -> JitFn { + <span class="kw">let </span><span class="kw-2">mut </span>bb = Asm::new(); + <span class="kw">let </span><span class="kw-2">mut </span>pc = <span class="self">self</span>.pc; + + <span class="lifetime">'outer</span>: <span class="kw">loop </span>{ + <span class="kw">let </span>insn = <span class="self">self</span>.imem[pc]; + + pc = pc.wrapping_add(<span class="number">1</span>); + + <span class="comment">// JIT ABI. + // enter + // rdi => regs + // rsi => dmem + // exit + // rax => JitRet(0, + // rdx => 1) + + // Generate memory operand into regs for guest register. + </span><span class="kw">let </span>reg_op = |r: TinyReg| { + MemOp::IndirectDisp(Reg64::rdi, (r.idx() * <span class="number">2</span>).try_into().expect(<span class="string">"only 3 regs"</span>)) + }; + + <span class="comment">// Generate memory operand into dmem for guest phys address. + </span><span class="kw">let </span>mem_op = |paddr: u16| MemOp::IndirectDisp(Reg64::rsi, paddr.into()); + + <span class="comment">// Compute instructions in translated basic block. + </span><span class="kw">let </span>bb_icnt = || -> u64 { (pc - <span class="self">self</span>.pc).try_into().unwrap() }; + + <span class="kw">let </span>reenter_pc = |pc: usize| -> u64 { pc.try_into().unwrap() }; + + <span class="kw">match </span>insn { + TinyInsn::Halt => { + bb.mov(Reg64::rax, Imm64::from(<span class="number">0</span>)); + bb.mov(Reg64::rdx, Imm64::from(bb_icnt())); + bb.ret(); + <span class="kw">break </span><span class="lifetime">'outer</span>; + } + TinyInsn::LoadImm(a, imm) => { + bb.mov(reg_op(a), Imm16::from(imm)); + } + TinyInsn::Load(a, addr) => { + bb.mov(Reg16::ax, mem_op(addr)); + bb.mov(reg_op(a), Reg16::ax); + } + TinyInsn::Store(a, addr) => { + bb.mov(Reg16::ax, reg_op(a)); + bb.mov(mem_op(addr), Reg16::ax); + } + TinyInsn::Add(a, b) => { + bb.mov(Reg16::ax, reg_op(b)); + bb.add(reg_op(a), Reg16::ax); + } + TinyInsn::Addi(a, imm) => { + bb.add(reg_op(a), Imm16::from(imm)); + } + TinyInsn::Branch(disp) => { + bb.mov(Reg64::rax, Imm64::from(bb_icnt())); + bb.mov(Reg64::rdx, Imm64::from(reenter_pc(disp))); + bb.ret(); + <span class="kw">break </span><span class="lifetime">'outer</span>; + } + TinyInsn::BranchZero(a, disp) => { + bb.cmp(reg_op(a), Imm16::from(<span class="number">0u16</span>)); + bb.mov(Reg64::rax, Imm64::from(bb_icnt())); + bb.mov(Reg64::rdx, Imm64::from(reenter_pc(disp))); + + <span class="kw">let </span><span class="kw-2">mut </span>skip_next_pc = Label::new(); + <span class="comment">// If register is zero, skip setting next pc as reenter pc. + </span>bb.jz(<span class="kw-2">&mut </span>skip_next_pc); + bb.mov(Reg64::rdx, Imm64::from(reenter_pc(pc))); + bb.bind(<span class="kw-2">&mut </span>skip_next_pc); + bb.ret(); + <span class="kw">break </span><span class="lifetime">'outer</span>; + } + } + } + + <span class="kw">unsafe </span>{ <span class="self">self</span>.rt.add_code::<JitFn>(bb.into_code()) } + } +} + +<span class="doccomment">/// A minial fixup utility to implement jump labels when constructing guest programs. +</span><span class="kw">pub struct </span>Fixup { + pc: usize, +} + +<span class="kw">impl </span>Fixup { + <span class="doccomment">/// Create a new `Fixup` at the current pc. + </span><span class="kw">pub fn </span>new(pc: usize) -> <span class="self">Self </span>{ + Fixup { pc } + } + + <span class="doccomment">/// Bind the `Fixup` to the current location of `prog` and resolve the `Fixup`. + </span><span class="kw">pub fn </span>bind(<span class="self">self</span>, prog: <span class="kw-2">&mut </span>Vec<TinyInsn>) { + <span class="kw">let </span>plen = prog.len(); + <span class="kw">let </span>insn = prog.get_mut(<span class="self">self</span>.pc).expect(<span class="kw-2">&</span><span class="macro">format!</span>( + <span class="string">"Trying to apply Fixup, but Fixup is out of range pc={} prog.len={}"</span>, + <span class="self">self</span>.pc, plen + )); + + <span class="kw">match </span>insn { + TinyInsn::Branch(disp) | TinyInsn::BranchZero(<span class="kw">_</span>, disp) => { + <span class="kw-2">*</span>disp = plen; + } + <span class="kw">_ </span>=> { + <span class="macro">unimplemented!</span>(<span class="string">"Trying to fixup non-branch instruction '{:?}'"</span>, <span class="kw-2">*</span>insn); + } + } + } +} + +<span class="doccomment">/// Generate a guest program to compute the fiibonacci sequence for `n`. +</span><span class="kw">pub fn </span>make_tinyvm_fib(start_n: u16) -> Vec<TinyInsn> { + <span class="comment">// Reference implementation: + // + // int fib(int n) + // int tmp = 0; + // int prv = 1; + // int sum = 0; + // loop: + // if (n == 0) goto end; + // tmp = sum; + // sum += prv; + // prv = tmp; + // --n; + // goto loop; + // end: + // return sum; + + // Variables live in memory, bin to fixed addresses. + </span><span class="kw">let </span>tmp = <span class="number">0u16</span>; + <span class="kw">let </span>prv = <span class="number">2u16</span>; + <span class="kw">let </span>sum = <span class="number">4u16</span>; + <span class="comment">// Loop counter mapped to register. + </span><span class="kw">let </span>n = TinyReg::C; + + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::with_capacity(<span class="number">32</span>); + + <span class="comment">// n = start_n + </span>prog.push(TinyInsn::LoadImm(n, start_n)); + + <span class="comment">// tmp = sum = 0 + </span>prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">0</span>)); + prog.push(TinyInsn::Store(TinyReg::A, tmp)); + prog.push(TinyInsn::Store(TinyReg::A, sum)); + + <span class="comment">// prv = 1 + </span>prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">1</span>)); + prog.push(TinyInsn::Store(TinyReg::A, prv)); + + <span class="comment">// Create loop_start label. + </span><span class="kw">let </span>loop_start = prog.len(); + + <span class="comment">// Create fixup to capture PC that need to be patched later. + </span><span class="kw">let </span>end_fixup = Fixup::new(prog.len()); + + <span class="comment">// if (n == 0) goto end + </span>prog.push(TinyInsn::BranchZero(n, <span class="number">0xdead</span>)); + + <span class="comment">// tmp = sum + </span>prog.push(TinyInsn::Load(TinyReg::A, sum)); + prog.push(TinyInsn::Store(TinyReg::A, tmp)); + + <span class="comment">// sum += prv + </span>prog.push(TinyInsn::Load(TinyReg::B, prv)); + prog.push(TinyInsn::Add(TinyReg::A, TinyReg::B)); + prog.push(TinyInsn::Store(TinyReg::A, sum)); + + <span class="comment">// prv = tmp + </span>prog.push(TinyInsn::Load(TinyReg::A, tmp)); + prog.push(TinyInsn::Store(TinyReg::A, prv)); + + <span class="comment">// --n + </span>prog.push(TinyInsn::Addi(n, -<span class="number">1</span>)); + + <span class="comment">// goto loop_start + </span>prog.push(TinyInsn::Branch(loop_start)); + + <span class="comment">// Bind end fixup to current PC, to patch branch to jump to here. + </span>end_fixup.bind(<span class="kw-2">&mut </span>prog); + + <span class="comment">// TinyReg::A = sum + </span>prog.push(TinyInsn::Load(TinyReg::A, sum)); + + <span class="comment">// Halt the VM. + </span>prog.push(TinyInsn::Halt); + + prog +} + +<span class="doccomment">/// Generate a test program for the jit. +</span><span class="kw">pub fn </span>make_tinyvm_jit_test() -> Vec<TinyInsn> { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::with_capacity(<span class="number">32</span>); + + prog.push(TinyInsn::Branch(<span class="number">1</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">0x0010</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::B, <span class="number">0x0</span>)); + + <span class="kw">let </span>start = prog.len(); + <span class="kw">let </span>end = Fixup::new(prog.len()); + prog.push(TinyInsn::BranchZero(TinyReg::A, <span class="number">0xdead</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::C, <span class="number">0x1</span>)); + prog.push(TinyInsn::Add(TinyReg::B, TinyReg::C)); + prog.push(TinyInsn::Addi(TinyReg::A, -<span class="number">1</span>)); + prog.push(TinyInsn::Branch(start)); + end.bind(<span class="kw-2">&mut </span>prog); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">0xabcd</span>)); + prog.push(TinyInsn::Store(TinyReg::A, <span class="number">0xffff</span>)); + prog.push(TinyInsn::Load(TinyReg::C, <span class="number">0xffff</span>)); + prog.push(TinyInsn::Halt); + prog.push(TinyInsn::Halt); + prog.push(TinyInsn::Halt); + prog.push(TinyInsn::Halt); + + prog +} + +<span class="doccomment">/// Generate a simple count down loop to crunch some instructions. +</span><span class="kw">pub fn </span>make_tinyvm_jit_perf() -> Vec<TinyInsn> { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::with_capacity(<span class="number">32</span>); + + prog.push(TinyInsn::Halt); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">0xffff</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::B, <span class="number">1</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::C, <span class="number">2</span>)); + prog.push(TinyInsn::Addi(TinyReg::A, -<span class="number">1</span>)); + prog.push(TinyInsn::BranchZero(TinyReg::A, <span class="number">0</span>)); + prog.push(TinyInsn::Branch(<span class="number">2</span>)); + prog +} + +<span class="kw">fn </span>main() { + <span class="kw">let </span>use_jit = <span class="kw">match </span>std::env::args().nth(<span class="number">1</span>) { + <span class="prelude-val">Some</span>(a) <span class="kw">if </span>a == <span class="string">"-h" </span>|| a == <span class="string">"--help" </span>=> { + <span class="macro">println!</span>(<span class="string">"Usage: tiny_vm [mode]"</span>); + <span class="macro">println!</span>(<span class="string">""</span>); + <span class="macro">println!</span>(<span class="string">"Options:"</span>); + <span class="macro">println!</span>(<span class="string">" mode if mode is 'jit' then run in jit mode, else in interpreter mode"</span>); + std::process::exit(<span class="number">0</span>); + } + <span class="prelude-val">Some</span>(a) <span class="kw">if </span>a == <span class="string">"jit" </span>=> <span class="bool-val">true</span>, + <span class="kw">_ </span>=> <span class="bool-val">false</span>, + }; + + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(make_tinyvm_fib(<span class="number">42</span>)); + + <span class="kw">if </span>use_jit { + <span class="macro">println!</span>(<span class="string">"Run in jit mode.."</span>); + vm.jit(); + } <span class="kw">else </span>{ + <span class="macro">println!</span>(<span class="string">"Run in interpreter mode.."</span>); + vm.interp(); + } + vm.dump(); +} + +<span class="attr">#[cfg(test)] +</span><span class="kw">mod </span>test { + <span class="kw">use super</span>::<span class="kw-2">*</span>; + + <span class="kw">fn </span>fib_rs(n: u64) -> u64 { + <span class="kw">if </span>n < <span class="number">2 </span>{ + n + } <span class="kw">else </span>{ + <span class="kw">let </span><span class="kw-2">mut </span>fib_n_m1 = <span class="number">0</span>; + <span class="kw">let </span><span class="kw-2">mut </span>fib_n = <span class="number">1</span>; + <span class="kw">for _ in </span><span class="number">1</span>..n { + <span class="kw">let </span>tmp = fib_n + fib_n_m1; + fib_n_m1 = fib_n; + fib_n = tmp; + } + fib_n + } + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_fib_interp() { + <span class="kw">for </span>n <span class="kw">in </span><span class="number">0</span>..<span class="number">92 </span>{ + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(make_tinyvm_fib(n)); + vm.interp(); + + <span class="macro">assert_eq!</span>((fib_rs(n <span class="kw">as </span>u64) & <span class="number">0xffff</span>) <span class="kw">as </span>u16, vm.read_reg(TinyReg::A)); + } + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_fib_jit() { + <span class="kw">for </span>n <span class="kw">in </span><span class="number">0</span>..<span class="number">92 </span>{ + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(make_tinyvm_fib(n)); + vm.jit(); + + <span class="macro">assert_eq!</span>((fib_rs(n <span class="kw">as </span>u64) & <span class="number">0xffff</span>) <span class="kw">as </span>u16, vm.read_reg(TinyReg::A)); + } + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_fib_icnt() { + <span class="kw">let </span><span class="kw-2">mut </span>vm1 = TinyVm::new(make_tinyvm_fib(<span class="number">91</span>)); + vm1.interp(); + <span class="kw">let </span><span class="kw-2">mut </span>vm2 = TinyVm::new(make_tinyvm_fib(<span class="number">91</span>)); + vm2.jit(); + + <span class="macro">assert_eq!</span>(vm1.icnt, vm2.icnt); + <span class="macro">assert_eq!</span>(vm1.pc, vm2.pc); + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_jit_load_imm() { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::new(); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">0x1111</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::B, <span class="number">0x2222</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::C, <span class="number">0x3333</span>)); + prog.push(TinyInsn::Halt); + + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(prog); + vm.jit(); + + <span class="macro">assert_eq!</span>(<span class="number">0x1111</span>, vm.read_reg(TinyReg::A)); + <span class="macro">assert_eq!</span>(<span class="number">0x2222</span>, vm.read_reg(TinyReg::B)); + <span class="macro">assert_eq!</span>(<span class="number">0x3333</span>, vm.read_reg(TinyReg::C)); + + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.icnt); + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.pc); + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_jit_add() { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::new(); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">0</span>)); + prog.push(TinyInsn::Addi(TinyReg::A, <span class="number">123</span>)); + + prog.push(TinyInsn::LoadImm(TinyReg::B, <span class="number">100</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::C, <span class="number">200</span>)); + prog.push(TinyInsn::Add(TinyReg::B, TinyReg::C)); + prog.push(TinyInsn::Halt); + + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(prog); + vm.jit(); + + <span class="macro">assert_eq!</span>(<span class="number">123</span>, vm.read_reg(TinyReg::A)); + <span class="macro">assert_eq!</span>(<span class="number">300</span>, vm.read_reg(TinyReg::B)); + <span class="macro">assert_eq!</span>(<span class="number">200</span>, vm.read_reg(TinyReg::C)); + + <span class="macro">assert_eq!</span>(<span class="number">6</span>, vm.icnt); + <span class="macro">assert_eq!</span>(<span class="number">6</span>, vm.pc); + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_jit_load_store() { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::new(); + prog.push(TinyInsn::Load(TinyReg::A, <span class="number">0xffff</span>)); + + prog.push(TinyInsn::LoadImm(TinyReg::B, <span class="number">0xf00d</span>)); + prog.push(TinyInsn::Store(TinyReg::B, <span class="number">0x8000</span>)); + prog.push(TinyInsn::Halt); + + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(prog); + vm.write_mem(PhysAddr(<span class="number">0xffff</span>), <span class="number">0xaabb</span>); + vm.jit(); + + <span class="macro">assert_eq!</span>(<span class="number">0xaabb</span>, vm.read_reg(TinyReg::A)); + <span class="macro">assert_eq!</span>(<span class="number">0xf00d</span>, vm.read_mem(PhysAddr(<span class="number">0x8000</span>))); + + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.icnt); + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.pc); + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_jit_branch() { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::new(); + prog.push(TinyInsn::Branch(<span class="number">2</span>)); + prog.push(TinyInsn::Halt); + prog.push(TinyInsn::Branch(<span class="number">6</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">1</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::B, <span class="number">2</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::C, <span class="number">3</span>)); + prog.push(TinyInsn::Branch(<span class="number">1</span>)); + + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(prog); + vm.jit(); + + <span class="macro">assert_eq!</span>(<span class="number">0</span>, vm.read_reg(TinyReg::A)); + <span class="macro">assert_eq!</span>(<span class="number">0</span>, vm.read_reg(TinyReg::B)); + <span class="macro">assert_eq!</span>(<span class="number">0</span>, vm.read_reg(TinyReg::C)); + + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.icnt); + <span class="macro">assert_eq!</span>(<span class="number">2</span>, vm.pc); + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_jit_branch_zero() { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::new(); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">1</span>)); + prog.push(TinyInsn::BranchZero(TinyReg::A, <span class="number">5</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">0</span>)); + prog.push(TinyInsn::BranchZero(TinyReg::A, <span class="number">5</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::B, <span class="number">22</span>)); + prog.push(TinyInsn::Halt); + + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(prog); + vm.jit(); + + <span class="macro">assert_eq!</span>(<span class="number">0</span>, vm.read_reg(TinyReg::A)); + <span class="macro">assert_eq!</span>(<span class="number">0</span>, vm.read_reg(TinyReg::B)); + <span class="macro">assert_eq!</span>(<span class="number">0</span>, vm.read_reg(TinyReg::C)); + + <span class="macro">assert_eq!</span>(<span class="number">5</span>, vm.icnt); + <span class="macro">assert_eq!</span>(<span class="number">6</span>, vm.pc); + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_mixed() { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::new(); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">100</span>)); + prog.push(TinyInsn::Add(TinyReg::B, TinyReg::A)); + prog.push(TinyInsn::Addi(TinyReg::C, <span class="number">100</span>)); + prog.push(TinyInsn::Halt); + + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(prog); + vm.interp(); + + <span class="macro">assert_eq!</span>(<span class="number">100</span>, vm.read_reg(TinyReg::A)); + <span class="macro">assert_eq!</span>(<span class="number">100</span>, vm.read_reg(TinyReg::B)); + <span class="macro">assert_eq!</span>(<span class="number">100</span>, vm.read_reg(TinyReg::C)); + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.icnt); + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.pc); + + vm.pc = <span class="number">0</span>; + vm.jit(); + + <span class="macro">assert_eq!</span>(<span class="number">100</span>, vm.read_reg(TinyReg::A)); + <span class="macro">assert_eq!</span>(<span class="number">200</span>, vm.read_reg(TinyReg::B)); + <span class="macro">assert_eq!</span>(<span class="number">200</span>, vm.read_reg(TinyReg::C)); + <span class="macro">assert_eq!</span>(<span class="number">8</span>, vm.icnt); + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.pc); + } +} +</code></pre></div></section></main></body></html>
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