diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/bf/bf.rs.html | 26 | ||||
| -rw-r--r-- | src/juicebox_asm/asm.rs.html | 148 | ||||
| -rw-r--r-- | src/juicebox_asm/insn/add.rs.html | 72 | ||||
| -rw-r--r-- | src/juicebox_asm/insn/cmp.rs.html | 10 | ||||
| -rw-r--r-- | src/juicebox_asm/insn/dec.rs.html | 18 | ||||
| -rw-r--r-- | src/juicebox_asm/insn/inc.rs.html | 18 | ||||
| -rw-r--r-- | src/juicebox_asm/insn/mov.rs.html | 38 | ||||
| -rw-r--r-- | src/juicebox_asm/insn/sub.rs.html | 8 | ||||
| -rw-r--r-- | src/juicebox_asm/insn/test.rs.html | 6 | ||||
| -rw-r--r-- | src/juicebox_asm/lib.rs.html | 154 | ||||
| -rw-r--r-- | src/juicebox_asm/mem.rs.html | 233 | ||||
| -rw-r--r-- | src/tiny_vm/tiny_vm.rs.html | 6 |
12 files changed, 426 insertions, 311 deletions
diff --git a/src/bf/bf.rs.html b/src/bf/bf.rs.html index 9bd6202..b29403b 100644 --- a/src/bf/bf.rs.html +++ b/src/bf/bf.rs.html @@ -333,7 +333,11 @@ <a href="#332" id="332">332</a> <a href="#333" id="333">333</a> <a href="#334" id="334">334</a> -<a href="#335" id="335">335</a></pre></div><pre class="rust"><code><span class="doccomment">//! Brainfuck VM. +<a href="#335" id="335">335</a> +<a href="#336" id="336">336</a> +<a href="#337" id="337">337</a> +<a href="#338" id="338">338</a> +<a href="#339" id="339">339</a></pre></div><pre class="rust"><code><span class="doccomment">//! Brainfuck VM. //! //! This example implements a simple //! [brainfuck](https://en.wikipedia.org/wiki/Brainfuck) interpreter @@ -354,7 +358,7 @@ <span class="kw">use </span>juicebox_asm::insn::<span class="kw-2">*</span>; <span class="kw">use </span>juicebox_asm::Runtime; -<span class="kw">use </span>juicebox_asm::{Asm, Imm64, Imm8, Label, MemOp, MemOp8, Reg64, Reg8}; +<span class="kw">use </span>juicebox_asm::{Asm, Imm64, Imm8, Label, Mem8, Reg64, Reg8}; <span class="comment">// -- BRAINFUCK INTERPRETER ---------------------------------------------------- @@ -539,12 +543,14 @@ // single add instruction during compile time. </span><span class="kw">match </span>vm.imem[pc..].iter().take_while(|&&i| i.eq(<span class="kw-2">&</span><span class="string">'+'</span>)).count() { - <span class="number">1 </span>=> asm.inc(MemOp8::from(MemOp::IndirectBaseIndex(dmem_base, dmem_idx))), + <span class="number">1 </span>=> { + asm.inc(Mem8::indirect_base_index(dmem_base, dmem_idx)); + } cnt <span class="kw">if </span>cnt <= i8::MAX <span class="kw">as </span>usize => { <span class="comment">// For add m64, imm8, the immediate is sign-extend and // hence treated as signed. </span>asm.add( - MemOp::IndirectBaseIndex(dmem_base, dmem_idx), + Mem8::indirect_base_index(dmem_base, dmem_idx), Imm8::from(cnt <span class="kw">as </span>u8), ); @@ -560,12 +566,14 @@ // single sub instruction during compile time. </span><span class="kw">match </span>vm.imem[pc..].iter().take_while(|&&i| i.eq(<span class="kw-2">&</span><span class="string">'-'</span>)).count() { - <span class="number">1 </span>=> asm.dec(MemOp8::from(MemOp::IndirectBaseIndex(dmem_base, dmem_idx))), + <span class="number">1 </span>=> { + asm.dec(Mem8::indirect_base_index(dmem_base, dmem_idx)); + } cnt <span class="kw">if </span>cnt <= i8::MAX <span class="kw">as </span>usize => { <span class="comment">// For sub m64, imm8, the immediate is sign-extend and // hence treated as signed. </span>asm.sub( - MemOp::IndirectBaseIndex(dmem_base, dmem_idx), + Mem8::indirect_base_index(dmem_base, dmem_idx), Imm8::from(cnt <span class="kw">as </span>u8), ); @@ -582,7 +590,7 @@ // then call into putchar. Since we stored all out vm state in // callee saved registers we don't need to save any registers // before the call. - </span>asm.mov(Reg8::dil, MemOp::IndirectBaseIndex(dmem_base, dmem_idx)); + </span>asm.mov(Reg8::dil, Mem8::indirect_base_index(dmem_base, dmem_idx)); asm.mov(Reg64::rax, Imm64::from(putchar <span class="kw">as </span>usize)); asm.call(Reg64::rax); } @@ -598,7 +606,7 @@ <span class="comment">// Goto label_pair.0 if data memory at active cell is 0. // if vm.dmem[vm.dptr] == 0 goto label_pair.0 </span>asm.cmp( - MemOp::IndirectBaseIndex(dmem_base, dmem_idx), + Mem8::indirect_base_index(dmem_base, dmem_idx), Imm8::from(<span class="number">0u8</span>), ); asm.jz(<span class="kw-2">&mut </span>label_pair.<span class="number">0</span>); @@ -615,7 +623,7 @@ <span class="comment">// Goto label_pair.1 if data memory at active cell is not 0. // if vm.dmem[vm.dptr] != 0 goto label_pair.1 </span>asm.cmp( - MemOp::IndirectBaseIndex(dmem_base, dmem_idx), + Mem8::indirect_base_index(dmem_base, dmem_idx), Imm8::from(<span class="number">0u8</span>), ); asm.jnz(<span class="kw-2">&mut </span>label_pair.<span class="number">1</span>); diff --git a/src/juicebox_asm/asm.rs.html b/src/juicebox_asm/asm.rs.html index 3f24ae2..1b159ca 100644 --- a/src/juicebox_asm/asm.rs.html +++ b/src/juicebox_asm/asm.rs.html @@ -450,17 +450,11 @@ <a href="#449" id="449">449</a> <a href="#450" id="450">450</a> <a href="#451" id="451">451</a> -<a href="#452" id="452">452</a> -<a href="#453" id="453">453</a> -<a href="#454" id="454">454</a> -<a href="#455" id="455">455</a> -<a href="#456" id="456">456</a> -<a href="#457" id="457">457</a> -<a href="#458" id="458">458</a> -<a href="#459" id="459">459</a></pre></div><pre class="rust"><code><span class="doccomment">//! The `x64` jit assembler. +<a href="#452" id="452">452</a></pre></div><pre class="rust"><code><span class="doccomment">//! The `x64` jit assembler. </span><span class="kw">use crate</span>::<span class="kw-2">*</span>; <span class="kw">use </span>imm::Imm; +<span class="kw">use </span>mem::{AddrMode, Mem}; <span class="kw">use </span>reg::Reg; <span class="doccomment">/// Encode the `REX` byte. @@ -614,24 +608,22 @@ } <span class="doccomment">/// Encode a memory operand instruction. - </span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_m<T: MemOpSized>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, opc_ext: u8, op1: T) + </span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_m<T: Mem>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, opc_ext: u8, op1: T) <span class="kw">where </span><span class="self">Self</span>: EncodeM<T>, { - <span class="kw">let </span>op1 = op1.mem_op(); - <span class="comment">// M operand encoding. // op1 -> modrm.rm - </span><span class="kw">let </span>(mode, rm) = <span class="kw">match </span>op1 { - MemOp::Indirect(..) => { + </span><span class="kw">let </span>(mode, rm) = <span class="kw">match </span>op1.mode() { + AddrMode::Indirect => { <span class="macro">assert!</span>(!op1.base().need_sib() && !op1.base().is_pc_rel()); (<span class="number">0b00</span>, op1.base().idx()) } - MemOp::IndirectDisp(..) => { + AddrMode::IndirectDisp => { <span class="macro">assert!</span>(!op1.base().need_sib()); (<span class="number">0b10</span>, op1.base().idx()) } - MemOp::IndirectBaseIndex(..) => { + AddrMode::IndirectBaseIndex => { <span class="macro">assert!</span>(!op1.base().is_pc_rel()); <span class="comment">// Using rsp as index register is interpreted as just base w/o offset. // https://wiki.osdev.org/X86-64_Instruction_Encoding#32.2F64-bit_addressing_2 @@ -652,31 +644,33 @@ <span class="self">self</span>.emit_optional(<span class="kw-2">&</span>[prefix, rex]); <span class="self">self</span>.emit(<span class="kw-2">&</span>[opc, modrm]); - <span class="kw">match </span>op1 { - MemOp::Indirect(..) => {} - MemOp::IndirectDisp(<span class="kw">_</span>, disp) => <span class="self">self</span>.emit(<span class="kw-2">&</span>disp.to_ne_bytes()), - MemOp::IndirectBaseIndex(base, index) => <span class="self">self</span>.emit(<span class="kw-2">&</span>[sib(<span class="number">0</span>, index.idx(), base.idx())]), + <span class="kw">match </span>op1.mode() { + AddrMode::Indirect => {} + AddrMode::IndirectDisp => <span class="self">self</span>.emit(<span class="kw-2">&</span>op1.disp().to_ne_bytes()), + AddrMode::IndirectBaseIndex => { + <span class="self">self</span>.emit(<span class="kw-2">&</span>[sib(<span class="number">0</span>, op1.index().idx(), op1.base().idx())]) + } } } <span class="doccomment">/// Encode a memory-immediate instruction. - </span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_mi<T: Imm>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, opc_ext: u8, op1: MemOp, op2: T) + </span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_mi<M: Mem, T: Imm>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, opc_ext: u8, op1: M, op2: T) <span class="kw">where - </span><span class="self">Self</span>: EncodeMI<T>, + </span><span class="self">Self</span>: EncodeMI<M>, { <span class="comment">// MI operand encoding. // op1 -> modrm.rm // op2 -> imm - </span><span class="kw">let </span>(mode, rm) = <span class="kw">match </span>op1 { - MemOp::Indirect(..) => { + </span><span class="kw">let </span>(mode, rm) = <span class="kw">match </span>op1.mode() { + AddrMode::Indirect => { <span class="macro">assert!</span>(!op1.base().need_sib() && !op1.base().is_pc_rel()); (<span class="number">0b00</span>, op1.base().idx()) } - MemOp::IndirectDisp(..) => { + AddrMode::IndirectDisp => { <span class="macro">assert!</span>(!op1.base().need_sib()); (<span class="number">0b10</span>, op1.base().idx()) } - MemOp::IndirectBaseIndex(..) => { + AddrMode::IndirectBaseIndex => { <span class="macro">assert!</span>(!op1.base().is_pc_rel()); <span class="comment">// Using rsp as index register is interpreted as just base w/o offset. // https://wiki.osdev.org/X86-64_Instruction_Encoding#32.2F64-bit_addressing_2 @@ -692,37 +686,39 @@ </span>rm, <span class="comment">/* rm */ </span>); - <span class="kw">let </span>prefix = <<span class="self">Self </span><span class="kw">as </span>EncodeMI<T>>::legacy_prefix(); - <span class="kw">let </span>rex = <<span class="self">Self </span><span class="kw">as </span>EncodeMI<T>>::rex(<span class="kw-2">&</span>op1); + <span class="kw">let </span>prefix = <<span class="self">Self </span><span class="kw">as </span>EncodeMI<M>>::legacy_prefix(); + <span class="kw">let </span>rex = <<span class="self">Self </span><span class="kw">as </span>EncodeMI<M>>::rex(<span class="kw-2">&</span>op1); <span class="self">self</span>.emit_optional(<span class="kw-2">&</span>[prefix, rex]); <span class="self">self</span>.emit(<span class="kw-2">&</span>[opc, modrm]); - <span class="kw">match </span>op1 { - MemOp::Indirect(..) => {} - MemOp::IndirectDisp(<span class="kw">_</span>, disp) => <span class="self">self</span>.emit(<span class="kw-2">&</span>disp.to_ne_bytes()), - MemOp::IndirectBaseIndex(base, index) => <span class="self">self</span>.emit(<span class="kw-2">&</span>[sib(<span class="number">0</span>, index.idx(), base.idx())]), + <span class="kw">match </span>op1.mode() { + AddrMode::Indirect => {} + AddrMode::IndirectDisp => <span class="self">self</span>.emit(<span class="kw-2">&</span>op1.disp().to_ne_bytes()), + AddrMode::IndirectBaseIndex => { + <span class="self">self</span>.emit(<span class="kw-2">&</span>[sib(<span class="number">0</span>, op1.index().idx(), op1.base().idx())]) + } } <span class="self">self</span>.emit(op2.bytes()); } <span class="doccomment">/// Encode a memory-register instruction. - </span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_mr<T: Reg>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, op1: MemOp, op2: T) + </span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_mr<M: Mem, T: Reg>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, op1: M, op2: T) <span class="kw">where - </span><span class="self">Self</span>: EncodeMR<T>, + </span><span class="self">Self</span>: EncodeMR<M>, { <span class="comment">// MR operand encoding. // op1 -> modrm.rm // op2 -> modrm.reg - </span><span class="kw">let </span>(mode, rm) = <span class="kw">match </span>op1 { - MemOp::Indirect(..) => { + </span><span class="kw">let </span>(mode, rm) = <span class="kw">match </span>op1.mode() { + AddrMode::Indirect => { <span class="macro">assert!</span>(!op1.base().need_sib() && !op1.base().is_pc_rel()); (<span class="number">0b00</span>, op1.base().idx()) } - MemOp::IndirectDisp(..) => { + AddrMode::IndirectDisp => { <span class="macro">assert!</span>(!op1.base().need_sib()); (<span class="number">0b10</span>, op1.base().idx()) } - MemOp::IndirectBaseIndex(..) => { + AddrMode::IndirectBaseIndex => { <span class="macro">assert!</span>(!op1.base().is_pc_rel()); <span class="comment">// Using rsp as index register is interpreted as just base w/o offset. // https://wiki.osdev.org/X86-64_Instruction_Encoding#32.2F64-bit_addressing_2 @@ -738,22 +734,24 @@ </span>rm, <span class="comment">/* rm */ </span>); - <span class="kw">let </span>prefix = <<span class="self">Self </span><span class="kw">as </span>EncodeMR<T>>::legacy_prefix(); - <span class="kw">let </span>rex = <<span class="self">Self </span><span class="kw">as </span>EncodeMR<T>>::rex(<span class="kw-2">&</span>op1, op2); + <span class="kw">let </span>prefix = <<span class="self">Self </span><span class="kw">as </span>EncodeMR<M>>::legacy_prefix(); + <span class="kw">let </span>rex = <<span class="self">Self </span><span class="kw">as </span>EncodeMR<M>>::rex(<span class="kw-2">&</span>op1, op2); <span class="self">self</span>.emit_optional(<span class="kw-2">&</span>[prefix, rex]); <span class="self">self</span>.emit(<span class="kw-2">&</span>[opc, modrm]); - <span class="kw">match </span>op1 { - MemOp::Indirect(..) => {} - MemOp::IndirectDisp(<span class="kw">_</span>, disp) => <span class="self">self</span>.emit(<span class="kw-2">&</span>disp.to_ne_bytes()), - MemOp::IndirectBaseIndex(base, index) => <span class="self">self</span>.emit(<span class="kw-2">&</span>[sib(<span class="number">0</span>, index.idx(), base.idx())]), + <span class="kw">match </span>op1.mode() { + AddrMode::Indirect => {} + AddrMode::IndirectDisp => <span class="self">self</span>.emit(<span class="kw-2">&</span>op1.disp().to_ne_bytes()), + AddrMode::IndirectBaseIndex => { + <span class="self">self</span>.emit(<span class="kw-2">&</span>[sib(<span class="number">0</span>, op1.index().idx(), op1.base().idx())]) + } } } <span class="doccomment">/// Encode a register-memory instruction. - </span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_rm<T: Reg>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, op1: T, op2: MemOp) + </span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">fn </span>encode_rm<T: Reg, M: Mem>(<span class="kw-2">&mut </span><span class="self">self</span>, opc: u8, op1: T, op2: M) <span class="kw">where - </span><span class="self">Self</span>: EncodeMR<T>, + </span><span class="self">Self</span>: EncodeMR<M>, { <span class="comment">// RM operand encoding. // op1 -> modrm.reg @@ -829,15 +827,15 @@ <span class="kw">impl </span>EncodeR<Reg64> <span class="kw">for </span>Asm {} <span class="doccomment">/// Encode helper for memory-register instructions. -</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">trait </span>EncodeMR<T: Reg> { +</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">trait </span>EncodeMR<M: Mem> { <span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> { <span class="prelude-val">None </span>} - <span class="kw">fn </span>rex(op1: <span class="kw-2">&</span>MemOp, op2: T) -> <span class="prelude-ty">Option</span><u8> { - <span class="kw">if </span>op2.need_rex() || op1.base().is_ext() || op1.index().is_ext() { + <span class="kw">fn </span>rex<T: Reg>(op1: <span class="kw-2">&</span>M, op2: T) -> <span class="prelude-ty">Option</span><u8> { + <span class="kw">if </span>M::is_64() || op2.is_ext() || op1.base().is_ext() || op1.index().is_ext() { <span class="prelude-val">Some</span>(rex( - op2.rexw(), + M::is_64(), op2.idx(), op1.index().idx(), op1.base().idx(), @@ -848,72 +846,60 @@ } } -<span class="kw">impl </span>EncodeMR<Reg8> <span class="kw">for </span>Asm {} -<span class="kw">impl </span>EncodeMR<Reg16> <span class="kw">for </span>Asm { +<span class="kw">impl </span>EncodeMR<Mem8> <span class="kw">for </span>Asm {} +<span class="kw">impl </span>EncodeMR<Mem16> <span class="kw">for </span>Asm { <span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> { <span class="prelude-val">Some</span>(<span class="number">0x66</span>) } } -<span class="kw">impl </span>EncodeMR<Reg32> <span class="kw">for </span>Asm {} -<span class="kw">impl </span>EncodeMR<Reg64> <span class="kw">for </span>Asm {} +<span class="kw">impl </span>EncodeMR<Mem32> <span class="kw">for </span>Asm {} +<span class="kw">impl </span>EncodeMR<Mem64> <span class="kw">for </span>Asm {} <span class="doccomment">/// Encode helper for memory-immediate instructions. -</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">trait </span>EncodeMI<T: Imm> { +</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">trait </span>EncodeMI<M: Mem> { <span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> { <span class="prelude-val">None </span>} - <span class="kw">fn </span>rex(op1: <span class="kw-2">&</span>MemOp) -> <span class="prelude-ty">Option</span><u8> { - <span class="kw">if </span>op1.base().is_ext() || op1.index().is_ext() { - <span class="prelude-val">Some</span>(rex(<span class="bool-val">false</span>, <span class="number">0</span>, op1.index().idx(), op1.base().idx())) + <span class="kw">fn </span>rex(op1: <span class="kw-2">&</span>M) -> <span class="prelude-ty">Option</span><u8> { + <span class="kw">if </span>M::is_64() || op1.base().is_ext() || op1.index().is_ext() { + <span class="prelude-val">Some</span>(rex(M::is_64(), <span class="number">0</span>, op1.index().idx(), op1.base().idx())) } <span class="kw">else </span>{ <span class="prelude-val">None </span>} } } -<span class="kw">impl </span>EncodeMI<Imm8> <span class="kw">for </span>Asm {} -<span class="kw">impl </span>EncodeMI<Imm16> <span class="kw">for </span>Asm { +<span class="kw">impl </span>EncodeMI<Mem8> <span class="kw">for </span>Asm {} +<span class="kw">impl </span>EncodeMI<Mem16> <span class="kw">for </span>Asm { <span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> { <span class="prelude-val">Some</span>(<span class="number">0x66</span>) } } -<span class="kw">impl </span>EncodeMI<Imm32> <span class="kw">for </span>Asm {} +<span class="kw">impl </span>EncodeMI<Mem32> <span class="kw">for </span>Asm {} +<span class="kw">impl </span>EncodeMI<Mem64> <span class="kw">for </span>Asm {} <span class="doccomment">/// Encode helper for memory operand instructions. -</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">trait </span>EncodeM<T: MemOpSized> { +</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">trait </span>EncodeM<M: Mem> { <span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> { <span class="prelude-val">None </span>} - <span class="kw">fn </span>rex(op1: <span class="kw-2">&</span>MemOp) -> <span class="prelude-ty">Option</span><u8> { - <span class="kw">if </span>op1.base().is_ext() || op1.index().is_ext() || <span class="self">Self</span>::is_64bit() { - <span class="prelude-val">Some</span>(rex( - <span class="self">Self</span>::is_64bit(), - <span class="number">0</span>, - op1.index().idx(), - op1.base().idx(), - )) + <span class="kw">fn </span>rex(op1: <span class="kw-2">&</span>M) -> <span class="prelude-ty">Option</span><u8> { + <span class="kw">if </span>M::is_64() || op1.base().is_ext() || op1.index().is_ext() { + <span class="prelude-val">Some</span>(rex(M::is_64(), <span class="number">0</span>, op1.index().idx(), op1.base().idx())) } <span class="kw">else </span>{ <span class="prelude-val">None </span>} } - - <span class="kw">fn </span>is_64bit() -> bool { - <span class="bool-val">false - </span>} } -<span class="kw">impl </span>EncodeM<MemOp8> <span class="kw">for </span>Asm {} -<span class="kw">impl </span>EncodeM<MemOp16> <span class="kw">for </span>Asm { +<span class="kw">impl </span>EncodeM<Mem8> <span class="kw">for </span>Asm {} +<span class="kw">impl </span>EncodeM<Mem16> <span class="kw">for </span>Asm { <span class="kw">fn </span>legacy_prefix() -> <span class="prelude-ty">Option</span><u8> { <span class="prelude-val">Some</span>(<span class="number">0x66</span>) } } -<span class="kw">impl </span>EncodeM<MemOp32> <span class="kw">for </span>Asm {} -<span class="kw">impl </span>EncodeM<MemOp64> <span class="kw">for </span>Asm { - <span class="kw">fn </span>is_64bit() -> bool { - <span class="bool-val">true - </span>} -} +<span class="kw">impl </span>EncodeM<Mem32> <span class="kw">for </span>Asm {} +<span class="kw">impl </span>EncodeM<Mem64> <span class="kw">for </span>Asm {} </code></pre></div></section></main></body></html>
\ No newline at end of file diff --git a/src/juicebox_asm/insn/add.rs.html b/src/juicebox_asm/insn/add.rs.html index f91aa25..be3d025 100644 --- a/src/juicebox_asm/insn/add.rs.html +++ b/src/juicebox_asm/insn/add.rs.html @@ -42,48 +42,84 @@ <a href="#41" id="41">41</a> <a href="#42" id="42">42</a> <a href="#43" id="43">43</a> -<a href="#44" id="44">44</a></pre></div><pre class="rust"><code><span class="kw">use </span><span class="kw">super</span>::Add; -<span class="kw">use crate</span>::{Asm, Imm16, Imm8, MemOp, Reg16, Reg32, Reg64}; +<a href="#44" id="44">44</a> +<a href="#45" id="45">45</a> +<a href="#46" id="46">46</a> +<a href="#47" id="47">47</a> +<a href="#48" id="48">48</a> +<a href="#49" id="49">49</a> +<a href="#50" id="50">50</a> +<a href="#51" id="51">51</a> +<a href="#52" id="52">52</a> +<a href="#53" id="53">53</a> +<a href="#54" id="54">54</a> +<a href="#55" id="55">55</a> +<a href="#56" id="56">56</a> +<a href="#57" id="57">57</a> +<a href="#58" id="58">58</a> +<a href="#59" id="59">59</a> +<a href="#60" id="60">60</a> +<a href="#61" id="61">61</a> +<a href="#62" id="62">62</a></pre></div><pre class="rust"><code><span class="kw">use </span><span class="kw">super</span>::Add; +<span class="kw">use crate</span>::{Asm, Imm16, Imm8, Mem16, Mem32, Mem64, Mem8, Reg16, Reg32, Reg64}; -<span class="kw">impl </span>Add<Reg64, Reg64> <span class="kw">for </span>Asm { - <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg64, op2: Reg64) { +<span class="kw">impl </span>Add<Reg32, Reg32> <span class="kw">for </span>Asm { + <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg32, op2: Reg32) { <span class="self">self</span>.encode_rr(<span class="kw-2">&</span>[<span class="number">0x01</span>], op1, op2); } } -<span class="kw">impl </span>Add<Reg32, Reg32> <span class="kw">for </span>Asm { - <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg32, op2: Reg32) { +<span class="kw">impl </span>Add<Reg64, Reg64> <span class="kw">for </span>Asm { + <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg64, op2: Reg64) { <span class="self">self</span>.encode_rr(<span class="kw-2">&</span>[<span class="number">0x01</span>], op1, op2); } } -<span class="kw">impl </span>Add<MemOp, Reg64> <span class="kw">for </span>Asm { - <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp, op2: Reg64) { +<span class="kw">impl </span>Add<Mem16, Reg16> <span class="kw">for </span>Asm { + <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem16, op2: Reg16) { <span class="self">self</span>.encode_mr(<span class="number">0x01</span>, op1, op2); } } -<span class="kw">impl </span>Add<MemOp, Reg16> <span class="kw">for </span>Asm { - <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp, op2: Reg16) { +<span class="kw">impl </span>Add<Mem64, Reg64> <span class="kw">for </span>Asm { + <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem64, op2: Reg64) { <span class="self">self</span>.encode_mr(<span class="number">0x01</span>, op1, op2); } } -<span class="kw">impl </span>Add<MemOp, Imm8> <span class="kw">for </span>Asm { - <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp, op2: Imm8) { +<span class="kw">impl </span>Add<Reg64, Mem64> <span class="kw">for </span>Asm { + <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg64, op2: Mem64) { + <span class="self">self</span>.encode_rm(<span class="number">0x03</span>, op1, op2); + } +} + +<span class="kw">impl </span>Add<Mem8, Imm8> <span class="kw">for </span>Asm { + <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem8, op2: Imm8) { + <span class="self">self</span>.encode_mi(<span class="number">0x80</span>, <span class="number">0</span>, op1, op2); + } +} + +<span class="kw">impl </span>Add<Mem16, Imm8> <span class="kw">for </span>Asm { + <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem16, op2: Imm8) { <span class="self">self</span>.encode_mi(<span class="number">0x83</span>, <span class="number">0</span>, op1, op2); } } -<span class="kw">impl </span>Add<MemOp, Imm16> <span class="kw">for </span>Asm { - <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp, op2: Imm16) { - <span class="self">self</span>.encode_mi(<span class="number">0x81</span>, <span class="number">0</span>, op1, op2); +<span class="kw">impl </span>Add<Mem32, Imm8> <span class="kw">for </span>Asm { + <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem32, op2: Imm8) { + <span class="self">self</span>.encode_mi(<span class="number">0x83</span>, <span class="number">0</span>, op1, op2); } } -<span class="kw">impl </span>Add<Reg64, MemOp> <span class="kw">for </span>Asm { - <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg64, op2: MemOp) { - <span class="self">self</span>.encode_rm(<span class="number">0x03</span>, op1, op2); +<span class="kw">impl </span>Add<Mem64, Imm8> <span class="kw">for </span>Asm { + <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem64, op2: Imm8) { + <span class="self">self</span>.encode_mi(<span class="number">0x83</span>, <span class="number">0</span>, op1, op2); + } +} + +<span class="kw">impl </span>Add<Mem16, Imm16> <span class="kw">for </span>Asm { + <span class="kw">fn </span>add(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem16, op2: Imm16) { + <span class="self">self</span>.encode_mi(<span class="number">0x81</span>, <span class="number">0</span>, op1, op2); } } </code></pre></div></section></main></body></html>
\ No newline at end of file diff --git a/src/juicebox_asm/insn/cmp.rs.html b/src/juicebox_asm/insn/cmp.rs.html index a4e5447..35bb5b7 100644 --- a/src/juicebox_asm/insn/cmp.rs.html +++ b/src/juicebox_asm/insn/cmp.rs.html @@ -13,16 +13,16 @@ <a href="#12" id="12">12</a> <a href="#13" id="13">13</a> <a href="#14" id="14">14</a></pre></div><pre class="rust"><code><span class="kw">use </span><span class="kw">super</span>::Cmp; -<span class="kw">use crate</span>::{Asm, Imm16, Imm8, MemOp}; +<span class="kw">use crate</span>::{Asm, Imm16, Imm8, Mem16, Mem8}; -<span class="kw">impl </span>Cmp<MemOp, Imm8> <span class="kw">for </span>Asm { - <span class="kw">fn </span>cmp(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp, op2: Imm8) { +<span class="kw">impl </span>Cmp<Mem8, Imm8> <span class="kw">for </span>Asm { + <span class="kw">fn </span>cmp(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem8, op2: Imm8) { <span class="self">self</span>.encode_mi(<span class="number">0x80</span>, <span class="number">0x7</span>, op1, op2); } } -<span class="kw">impl </span>Cmp<MemOp, Imm16> <span class="kw">for </span>Asm { - <span class="kw">fn </span>cmp(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp, op2: Imm16) { +<span class="kw">impl </span>Cmp<Mem16, Imm16> <span class="kw">for </span>Asm { + <span class="kw">fn </span>cmp(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem16, op2: Imm16) { <span class="self">self</span>.encode_mi(<span class="number">0x81</span>, <span class="number">0x7</span>, op1, op2); } } diff --git a/src/juicebox_asm/insn/dec.rs.html b/src/juicebox_asm/insn/dec.rs.html index 7a05154..4bd9216 100644 --- a/src/juicebox_asm/insn/dec.rs.html +++ b/src/juicebox_asm/insn/dec.rs.html @@ -37,7 +37,7 @@ <a href="#36" id="36">36</a> <a href="#37" id="37">37</a> <a href="#38" id="38">38</a></pre></div><pre class="rust"><code><span class="kw">use </span><span class="kw">super</span>::Dec; -<span class="kw">use crate</span>::{Asm, MemOp16, MemOp32, MemOp64, MemOp8, Reg32, Reg64}; +<span class="kw">use crate</span>::{Asm, Mem16, Mem32, Mem64, Mem8, Reg32, Reg64}; <span class="kw">impl </span>Dec<Reg64> <span class="kw">for </span>Asm { <span class="kw">fn </span>dec(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg64) { @@ -51,26 +51,26 @@ } } -<span class="kw">impl </span>Dec<MemOp8> <span class="kw">for </span>Asm { - <span class="kw">fn </span>dec(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp8) { +<span class="kw">impl </span>Dec<Mem8> <span class="kw">for </span>Asm { + <span class="kw">fn </span>dec(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem8) { <span class="self">self</span>.encode_m(<span class="number">0xfe</span>, <span class="number">1</span>, op1); } } -<span class="kw">impl </span>Dec<MemOp16> <span class="kw">for </span>Asm { - <span class="kw">fn </span>dec(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp16) { +<span class="kw">impl </span>Dec<Mem16> <span class="kw">for </span>Asm { + <span class="kw">fn </span>dec(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem16) { <span class="self">self</span>.encode_m(<span class="number">0xff</span>, <span class="number">1</span>, op1); } } -<span class="kw">impl </span>Dec<MemOp32> <span class="kw">for </span>Asm { - <span class="kw">fn </span>dec(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp32) { +<span class="kw">impl </span>Dec<Mem32> <span class="kw">for </span>Asm { + <span class="kw">fn </span>dec(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem32) { <span class="self">self</span>.encode_m(<span class="number">0xff</span>, <span class="number">1</span>, op1); } } -<span class="kw">impl </span>Dec<MemOp64> <span class="kw">for </span>Asm { - <span class="kw">fn </span>dec(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp64) { +<span class="kw">impl </span>Dec<Mem64> <span class="kw">for </span>Asm { + <span class="kw">fn </span>dec(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem64) { <span class="self">self</span>.encode_m(<span class="number">0xff</span>, <span class="number">1</span>, op1); } } diff --git a/src/juicebox_asm/insn/inc.rs.html b/src/juicebox_asm/insn/inc.rs.html index 05ce6bb..c559c66 100644 --- a/src/juicebox_asm/insn/inc.rs.html +++ b/src/juicebox_asm/insn/inc.rs.html @@ -37,7 +37,7 @@ <a href="#36" id="36">36</a> <a href="#37" id="37">37</a> <a href="#38" id="38">38</a></pre></div><pre class="rust"><code><span class="kw">use </span><span class="kw">super</span>::Inc; -<span class="kw">use crate</span>::{Asm, MemOp16, MemOp32, MemOp64, MemOp8, Reg32, Reg64}; +<span class="kw">use crate</span>::{Asm, Mem16, Mem32, Mem64, Mem8, Reg32, Reg64}; <span class="kw">impl </span>Inc<Reg64> <span class="kw">for </span>Asm { <span class="kw">fn </span>inc(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg64) { @@ -51,26 +51,26 @@ } } -<span class="kw">impl </span>Inc<MemOp8> <span class="kw">for </span>Asm { - <span class="kw">fn </span>inc(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp8) { +<span class="kw">impl </span>Inc<Mem8> <span class="kw">for </span>Asm { + <span class="kw">fn </span>inc(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem8) { <span class="self">self</span>.encode_m(<span class="number">0xfe</span>, <span class="number">0</span>, op1); } } -<span class="kw">impl </span>Inc<MemOp16> <span class="kw">for </span>Asm { - <span class="kw">fn </span>inc(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp16) { +<span class="kw">impl </span>Inc<Mem16> <span class="kw">for </span>Asm { + <span class="kw">fn </span>inc(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem16) { <span class="self">self</span>.encode_m(<span class="number">0xff</span>, <span class="number">0</span>, op1); } } -<span class="kw">impl </span>Inc<MemOp32> <span class="kw">for </span>Asm { - <span class="kw">fn </span>inc(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp32) { +<span class="kw">impl </span>Inc<Mem32> <span class="kw">for </span>Asm { + <span class="kw">fn </span>inc(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem32) { <span class="self">self</span>.encode_m(<span class="number">0xff</span>, <span class="number">0</span>, op1); } } -<span class="kw">impl </span>Inc<MemOp64> <span class="kw">for </span>Asm { - <span class="kw">fn </span>inc(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp64) { +<span class="kw">impl </span>Inc<Mem64> <span class="kw">for </span>Asm { + <span class="kw">fn </span>inc(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem64) { <span class="self">self</span>.encode_m(<span class="number">0xff</span>, <span class="number">0</span>, op1); } } diff --git a/src/juicebox_asm/insn/mov.rs.html b/src/juicebox_asm/insn/mov.rs.html index 5bd4111..ab91c85 100644 --- a/src/juicebox_asm/insn/mov.rs.html +++ b/src/juicebox_asm/insn/mov.rs.html @@ -113,7 +113,7 @@ <a href="#112" id="112">112</a> <a href="#113" id="113">113</a> <a href="#114" id="114">114</a></pre></div><pre class="rust"><code><span class="kw">use </span><span class="kw">super</span>::Mov; -<span class="kw">use crate</span>::{Asm, Imm16, Imm32, Imm64, Imm8, MemOp, Reg16, Reg32, Reg64, Reg8}; +<span class="kw">use crate</span>::{Asm, Imm16, Imm32, Imm64, Imm8, Mem16, Mem32, Mem64, Mem8, Reg16, Reg32, Reg64, Reg8}; <span class="comment">// -- MOV : reg reg @@ -143,52 +143,52 @@ <span class="comment">// -- MOV : mem reg -</span><span class="kw">impl </span>Mov<MemOp, Reg64> <span class="kw">for </span>Asm { - <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp, op2: Reg64) { +</span><span class="kw">impl </span>Mov<Mem64, Reg64> <span class="kw">for </span>Asm { + <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem64, op2: Reg64) { <span class="self">self</span>.encode_mr(<span class="number">0x89</span>, op1, op2); } } -<span class="kw">impl </span>Mov<MemOp, Reg32> <span class="kw">for </span>Asm { - <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp, op2: Reg32) { +<span class="kw">impl </span>Mov<Mem32, Reg32> <span class="kw">for </span>Asm { + <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem32, op2: Reg32) { <span class="self">self</span>.encode_mr(<span class="number">0x89</span>, op1, op2); } } -<span class="kw">impl </span>Mov<MemOp, Reg16> <span class="kw">for </span>Asm { - <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp, op2: Reg16) { +<span class="kw">impl </span>Mov<Mem16, Reg16> <span class="kw">for </span>Asm { + <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem16, op2: Reg16) { <span class="self">self</span>.encode_mr(<span class="number">0x89</span>, op1, op2); } } -<span class="kw">impl </span>Mov<MemOp, Reg8> <span class="kw">for </span>Asm { - <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp, op2: Reg8) { +<span class="kw">impl </span>Mov<Mem8, Reg8> <span class="kw">for </span>Asm { + <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem8, op2: Reg8) { <span class="self">self</span>.encode_mr(<span class="number">0x88</span>, op1, op2); } } <span class="comment">// -- MOV : reg mem -</span><span class="kw">impl </span>Mov<Reg64, MemOp> <span class="kw">for </span>Asm { - <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg64, op2: MemOp) { +</span><span class="kw">impl </span>Mov<Reg64, Mem64> <span class="kw">for </span>Asm { + <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg64, op2: Mem64) { <span class="self">self</span>.encode_rm(<span class="number">0x8b</span>, op1, op2); } } -<span class="kw">impl </span>Mov<Reg32, MemOp> <span class="kw">for </span>Asm { - <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg32, op2: MemOp) { +<span class="kw">impl </span>Mov<Reg32, Mem32> <span class="kw">for </span>Asm { + <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg32, op2: Mem32) { <span class="self">self</span>.encode_rm(<span class="number">0x8b</span>, op1, op2); } } -<span class="kw">impl </span>Mov<Reg16, MemOp> <span class="kw">for </span>Asm { - <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg16, op2: MemOp) { +<span class="kw">impl </span>Mov<Reg16, Mem16> <span class="kw">for </span>Asm { + <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg16, op2: Mem16) { <span class="self">self</span>.encode_rm(<span class="number">0x8b</span>, op1, op2); } } -<span class="kw">impl </span>Mov<Reg8, MemOp> <span class="kw">for </span>Asm { - <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg8, op2: MemOp) { +<span class="kw">impl </span>Mov<Reg8, Mem8> <span class="kw">for </span>Asm { + <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg8, op2: Mem8) { <span class="self">self</span>.encode_rm(<span class="number">0x8a</span>, op1, op2); } } @@ -221,8 +221,8 @@ <span class="comment">// -- MOV : mem imm -</span><span class="kw">impl </span>Mov<MemOp, Imm16> <span class="kw">for </span>Asm { - <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp, op2: Imm16) { +</span><span class="kw">impl </span>Mov<Mem16, Imm16> <span class="kw">for </span>Asm { + <span class="kw">fn </span>mov(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem16, op2: Imm16) { <span class="self">self</span>.encode_mi(<span class="number">0xc7</span>, <span class="number">0</span>, op1, op2); } } diff --git a/src/juicebox_asm/insn/sub.rs.html b/src/juicebox_asm/insn/sub.rs.html index f350d05..b385a09 100644 --- a/src/juicebox_asm/insn/sub.rs.html +++ b/src/juicebox_asm/insn/sub.rs.html @@ -13,7 +13,7 @@ <a href="#12" id="12">12</a> <a href="#13" id="13">13</a> <a href="#14" id="14">14</a></pre></div><pre class="rust"><code><span class="kw">use </span><span class="kw">super</span>::Sub; -<span class="kw">use crate</span>::{Asm, Imm8, MemOp, Reg64}; +<span class="kw">use crate</span>::{Asm, Imm8, Mem8, Reg64}; <span class="kw">impl </span>Sub<Reg64, Reg64> <span class="kw">for </span>Asm { <span class="kw">fn </span>sub(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg64, op2: Reg64) { @@ -21,9 +21,9 @@ } } -<span class="kw">impl </span>Sub<MemOp, Imm8> <span class="kw">for </span>Asm { - <span class="kw">fn </span>sub(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp, op2: Imm8) { - <span class="self">self</span>.encode_mi(<span class="number">0x83</span>, <span class="number">5</span>, op1, op2); +<span class="kw">impl </span>Sub<Mem8, Imm8> <span class="kw">for </span>Asm { + <span class="kw">fn </span>sub(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem8, op2: Imm8) { + <span class="self">self</span>.encode_mi(<span class="number">0x80</span>, <span class="number">5</span>, op1, op2); } } </code></pre></div></section></main></body></html>
\ No newline at end of file diff --git a/src/juicebox_asm/insn/test.rs.html b/src/juicebox_asm/insn/test.rs.html index 4c9bd7d..32339bc 100644 --- a/src/juicebox_asm/insn/test.rs.html +++ b/src/juicebox_asm/insn/test.rs.html @@ -19,7 +19,7 @@ <a href="#18" id="18">18</a> <a href="#19" id="19">19</a> <a href="#20" id="20">20</a></pre></div><pre class="rust"><code><span class="kw">use </span><span class="kw">super</span>::Test; -<span class="kw">use crate</span>::{Asm, Imm16, MemOp, Reg32, Reg64}; +<span class="kw">use crate</span>::{Asm, Imm16, Mem16, Reg32, Reg64}; <span class="kw">impl </span>Test<Reg64, Reg64> <span class="kw">for </span>Asm { <span class="kw">fn </span>test(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Reg64, op2: Reg64) { @@ -33,8 +33,8 @@ } } -<span class="kw">impl </span>Test<MemOp, Imm16> <span class="kw">for </span>Asm { - <span class="kw">fn </span>test(<span class="kw-2">&mut </span><span class="self">self</span>, op1: MemOp, op2: Imm16) { +<span class="kw">impl </span>Test<Mem16, Imm16> <span class="kw">for </span>Asm { + <span class="kw">fn </span>test(<span class="kw-2">&mut </span><span class="self">self</span>, op1: Mem16, op2: Imm16) { <span class="self">self</span>.encode_mi(<span class="number">0xf7</span>, <span class="number">0</span>, op1, op2); } } diff --git a/src/juicebox_asm/lib.rs.html b/src/juicebox_asm/lib.rs.html index 2b9ed8a..4b32e80 100644 --- a/src/juicebox_asm/lib.rs.html +++ b/src/juicebox_asm/lib.rs.html @@ -88,81 +88,7 @@ <a href="#87" id="87">87</a> <a href="#88" id="88">88</a> <a href="#89" id="89">89</a> -<a href="#90" id="90">90</a> -<a href="#91" id="91">91</a> -<a href="#92" id="92">92</a> -<a href="#93" id="93">93</a> -<a href="#94" id="94">94</a> -<a href="#95" id="95">95</a> -<a href="#96" id="96">96</a> -<a href="#97" id="97">97</a> -<a href="#98" id="98">98</a> -<a href="#99" id="99">99</a> -<a href="#100" id="100">100</a> -<a href="#101" id="101">101</a> -<a href="#102" id="102">102</a> -<a href="#103" id="103">103</a> -<a href="#104" id="104">104</a> -<a href="#105" id="105">105</a> -<a href="#106" id="106">106</a> -<a href="#107" id="107">107</a> -<a href="#108" id="108">108</a> -<a href="#109" id="109">109</a> -<a href="#110" id="110">110</a> -<a href="#111" id="111">111</a> -<a href="#112" id="112">112</a> -<a href="#113" id="113">113</a> -<a href="#114" id="114">114</a> -<a href="#115" id="115">115</a> -<a href="#116" id="116">116</a> -<a href="#117" id="117">117</a> -<a href="#118" id="118">118</a> -<a href="#119" id="119">119</a> -<a href="#120" id="120">120</a> -<a href="#121" id="121">121</a> -<a href="#122" id="122">122</a> -<a href="#123" id="123">123</a> -<a href="#124" id="124">124</a> -<a href="#125" id="125">125</a> -<a href="#126" id="126">126</a> -<a href="#127" id="127">127</a> -<a href="#128" id="128">128</a> -<a href="#129" id="129">129</a> -<a href="#130" id="130">130</a> -<a href="#131" id="131">131</a> -<a href="#132" id="132">132</a> -<a href="#133" id="133">133</a> -<a href="#134" id="134">134</a> -<a href="#135" id="135">135</a> -<a href="#136" id="136">136</a> -<a href="#137" id="137">137</a> -<a href="#138" id="138">138</a> -<a href="#139" id="139">139</a> -<a href="#140" id="140">140</a> -<a href="#141" id="141">141</a> -<a href="#142" id="142">142</a> -<a href="#143" id="143">143</a> -<a href="#144" id="144">144</a> -<a href="#145" id="145">145</a> -<a href="#146" id="146">146</a> -<a href="#147" id="147">147</a> -<a href="#148" id="148">148</a> -<a href="#149" id="149">149</a> -<a href="#150" id="150">150</a> -<a href="#151" id="151">151</a> -<a href="#152" id="152">152</a> -<a href="#153" id="153">153</a> -<a href="#154" id="154">154</a> -<a href="#155" id="155">155</a> -<a href="#156" id="156">156</a> -<a href="#157" id="157">157</a> -<a href="#158" id="158">158</a> -<a href="#159" id="159">159</a> -<a href="#160" id="160">160</a> -<a href="#161" id="161">161</a> -<a href="#162" id="162">162</a> -<a href="#163" id="163">163</a> -<a href="#164" id="164">164</a></pre></div><pre class="rust"><code><span class="doccomment">//! A simple `x64` jit assembler with a minimal runtime to execute emitted code for fun. +<a href="#90" id="90">90</a></pre></div><pre class="rust"><code><span class="doccomment">//! A simple `x64` jit assembler with a minimal runtime to execute emitted code for fun. //! //! The following is an fibonacci example implementation. //! ```rust @@ -240,6 +166,7 @@ </span><span class="kw">mod </span>asm; <span class="kw">mod </span>imm; <span class="kw">mod </span>label; +<span class="kw">mod </span>mem; <span class="kw">mod </span>reg; <span class="kw">mod </span>rt; @@ -248,82 +175,7 @@ <span class="kw">pub use </span>asm::Asm; <span class="kw">pub use </span>imm::{Imm16, Imm32, Imm64, Imm8}; <span class="kw">pub use </span>label::Label; +<span class="kw">pub use </span>mem::{Mem16, Mem32, Mem64, Mem8}; <span class="kw">pub use </span>reg::{Reg16, Reg32, Reg64, Reg8}; <span class="kw">pub use </span>rt::Runtime; - -<span class="doccomment">/// Type representing a memory operand. -</span><span class="attr">#[derive(Clone, Copy)] -</span><span class="kw">pub enum </span>MemOp { - <span class="doccomment">/// An indirect memory operand, eg `mov [rax], rcx`. - </span>Indirect(Reg64), - - <span class="doccomment">/// An indirect memory operand with additional displacement, eg `mov [rax + 0x10], rcx`. - </span>IndirectDisp(Reg64, i32), - - <span class="doccomment">/// An indirect memory operand in the form base + index, eg `mov [rax + rcx], rdx`. - </span>IndirectBaseIndex(Reg64, Reg64), -} - -<span class="kw">impl </span>MemOp { - <span class="doccomment">/// Get the base address register of the memory operand. - </span><span class="kw">const fn </span>base(<span class="kw-2">&</span><span class="self">self</span>) -> Reg64 { - <span class="kw">match </span><span class="self">self </span>{ - MemOp::Indirect(base) => <span class="kw-2">*</span>base, - MemOp::IndirectDisp(base, ..) => <span class="kw-2">*</span>base, - MemOp::IndirectBaseIndex(base, ..) => <span class="kw-2">*</span>base, - } - } - - <span class="doccomment">/// Get the index register of the memory operand. - </span><span class="kw">fn </span>index(<span class="kw-2">&</span><span class="self">self</span>) -> Reg64 { - <span class="comment">// Return zero index register for memory operands w/o index register. - </span><span class="kw">let </span>zero_index = Reg64::rax; - <span class="kw">use </span>reg::Reg; - <span class="macro">assert_eq!</span>(zero_index.idx(), <span class="number">0</span>); - - <span class="kw">match </span><span class="self">self </span>{ - MemOp::Indirect(..) => zero_index, - MemOp::IndirectDisp(..) => zero_index, - MemOp::IndirectBaseIndex(.., index) => <span class="kw-2">*</span>index, - } - } -} - -<span class="doccomment">/// Trait to give size hints for memory operands. -</span><span class="kw">trait </span>MemOpSized { - <span class="kw">fn </span>mem_op(<span class="kw-2">&</span><span class="self">self</span>) -> MemOp; -} - -<span class="macro">macro_rules!</span> impl_memop_sized { - ($(<span class="attr">#[<span class="macro-nonterminal">$doc</span>:meta] </span><span class="macro-nonterminal">$name</span>:ident)+) => { - $( - <span class="attr">#[<span class="macro-nonterminal">$doc</span>] - </span><span class="kw">pub struct </span><span class="macro-nonterminal">$name</span>(MemOp); - - <span class="kw">impl </span><span class="macro-nonterminal">$name </span>{ - <span class="doccomment">/// Create a memory with size hint from a raw memory operand. - </span><span class="kw">pub fn </span>from(op: MemOp) -> <span class="self">Self </span>{ - <span class="self">Self</span>(op) - } - } - - <span class="kw">impl </span>MemOpSized <span class="kw">for </span><span class="macro-nonterminal">$name </span>{ - <span class="kw">fn </span>mem_op(<span class="kw-2">&</span><span class="self">self</span>) -> MemOp { - <span class="self">self</span>.<span class="number">0 - </span>} - } - )+ - }; -} - -<span class="macro">impl_memop_sized!</span>( - <span class="doccomment">/// A memory operand with a word (8 bit) size hint. - </span>MemOp8 - <span class="doccomment">/// A memory operand with a word (16 bit) size hint. - </span>MemOp16 - <span class="doccomment">/// A memory operand with a dword (32 bit) size hint. - </span>MemOp32 - <span class="doccomment">/// A memory operand with a qword (64 bit) size hint. - </span>MemOp64 -); </code></pre></div></section></main></body></html>
\ No newline at end of file diff --git a/src/juicebox_asm/mem.rs.html b/src/juicebox_asm/mem.rs.html new file mode 100644 index 0000000..7212af9 --- /dev/null +++ b/src/juicebox_asm/mem.rs.html @@ -0,0 +1,233 @@ +<!DOCTYPE html><html lang="en"><head><meta charset="utf-8"><meta name="viewport" content="width=device-width, initial-scale=1.0"><meta name="generator" content="rustdoc"><meta name="description" content="Source of the Rust file `src/mem.rs`."><title>mem.rs - source</title><script>if(window.location.protocol!=="file:")document.head.insertAdjacentHTML("beforeend","SourceSerif4-Regular-46f98efaafac5295.ttf.woff2,FiraSans-Regular-018c141bf0843ffd.woff2,FiraSans-Medium-8f9a781e4970d388.woff2,SourceCodePro-Regular-562dcc5011b6de7d.ttf.woff2,SourceCodePro-Semibold-d899c5a5c4aeb14a.ttf.woff2".split(",").map(f=>`<link rel="preload" as="font" type="font/woff2" crossorigin href="../../static.files/${f}">`).join(""))</script><link rel="stylesheet" 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id="112">112</a> +<a href="#113" id="113">113</a> +<a href="#114" id="114">114</a> +<a href="#115" id="115">115</a> +<a href="#116" id="116">116</a></pre></div><pre class="rust"><code><span class="doccomment">//! Definition of different addressing modes and memory operande used as input +//! and ouput operands in various instructions. + +</span><span class="kw">use </span><span class="kw">crate</span>::Reg64; + +<span class="attr">#[derive(Clone, Copy)] +</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">enum </span>AddrMode { + <span class="doccomment">/// An indirect memory operand, eg `mov [rax], rcx`. + </span>Indirect, + <span class="doccomment">/// An indirect memory operand with additional displacement, eg `mov [rax + 0x10], rcx`. + </span>IndirectDisp, + <span class="doccomment">/// An indirect memory operand in the form base + index, eg `mov [rax + rcx], rdx`. + </span>IndirectBaseIndex, +} + +<span class="doccomment">/// Trait to interact with memory operands. +</span><span class="kw">pub</span>(<span class="kw">crate</span>) <span class="kw">trait </span>Mem { + <span class="doccomment">/// Get the addressing mode [`AddrMode`] of the memory operand. + </span><span class="kw">fn </span>mode(<span class="kw-2">&</span><span class="self">self</span>) -> AddrMode; + + <span class="doccomment">/// Get the base address register of the memory operand. + </span><span class="kw">fn </span>base(<span class="kw-2">&</span><span class="self">self</span>) -> Reg64; + + <span class="doccomment">/// Get the index register of the memory operand. + </span><span class="kw">fn </span>index(<span class="kw-2">&</span><span class="self">self</span>) -> Reg64; + + <span class="doccomment">/// Get the displacement of the memory operand. + </span><span class="kw">fn </span>disp(<span class="kw-2">&</span><span class="self">self</span>) -> i32; + + <span class="doccomment">/// Check if memory operand is 64 bit. + </span><span class="kw">fn </span>is_64() -> bool; +} + +<span class="macro">macro_rules!</span> impl_mem { + ($(<span class="attr">#[<span class="macro-nonterminal">$doc</span>:meta] </span><span class="macro-nonterminal">$name</span>:ident)+) => { + $( + <span class="attr">#[<span class="macro-nonterminal">$doc</span>] + </span><span class="kw">pub struct </span><span class="macro-nonterminal">$name </span>{ + mode: AddrMode, + base: Reg64, + index: Reg64, + disp: i32, + } + + <span class="kw">impl </span>Mem <span class="kw">for </span><span class="macro-nonterminal">$name </span>{ + <span class="kw">fn </span>mode(<span class="kw-2">&</span><span class="self">self</span>) -> AddrMode { + <span class="self">self</span>.mode + } + + <span class="kw">fn </span>base(<span class="kw-2">&</span><span class="self">self</span>) -> Reg64 { + <span class="self">self</span>.base + } + + <span class="kw">fn </span>index(<span class="kw-2">&</span><span class="self">self</span>) -> Reg64 { + <span class="self">self</span>.index + } + + <span class="kw">fn </span>disp(<span class="kw-2">&</span><span class="self">self</span>) -> i32 { + <span class="self">self</span>.disp + } + + <span class="kw">fn </span>is_64() -> bool { + <span class="kw">use </span>std::any::TypeId; + TypeId::of::<<span class="self">Self</span>>() == TypeId::of::<Mem64>() + } + } + + <span class="kw">impl </span><span class="macro-nonterminal">$name </span>{ + <span class="doccomment">/// Create a memory operand with `indirect` addressing mode. + /// For example `mov [rax], rcx`. + </span><span class="kw">pub fn </span>indirect(base: Reg64) -> <span class="self">Self </span>{ + <span class="self">Self </span>{ + mode: AddrMode::Indirect, + base, + index: Reg64::rax, <span class="comment">/* zero index */ + </span>disp: <span class="number">0</span>, + } + } + + <span class="doccomment">/// Create a memory operand with `indirect + displacement` + /// addressing mode. + /// For example `mov [rax + 0x10], rcx`. + </span><span class="kw">pub fn </span>indirect_disp(base: Reg64, disp: i32) -> <span class="self">Self </span>{ + <span class="self">Self </span>{ + mode: AddrMode::IndirectDisp, + base, + index: Reg64::rax, <span class="comment">/* zero index */ + </span>disp, + } + } + + <span class="doccomment">/// Create a memory operand with `base + index` addressing mode. + /// For example `mov [rax + rcx], rdx`. + </span><span class="kw">pub fn </span>indirect_base_index(base: Reg64, index: Reg64) -> <span class="self">Self </span>{ + <span class="self">Self </span>{ + mode: AddrMode::IndirectBaseIndex, + base, + index, + disp: <span class="number">0</span>, + } + } + } + )+ + } +} + +<span class="macro">impl_mem!</span>( + <span class="doccomment">/// A memory operand with `byte` size (8 bit). + </span>Mem8 + <span class="doccomment">/// A memory operand with `word` size (16 bit). + </span>Mem16 + <span class="doccomment">/// A memory operand with `dword` size (32 bit). + </span>Mem32 + <span class="doccomment">/// A memory operand with `qword` size (64 bit). + </span>Mem64 +); +</code></pre></div></section></main></body></html>
\ No newline at end of file diff --git a/src/tiny_vm/tiny_vm.rs.html b/src/tiny_vm/tiny_vm.rs.html index 13c5a44..8062aa5 100644 --- a/src/tiny_vm/tiny_vm.rs.html +++ b/src/tiny_vm/tiny_vm.rs.html @@ -743,7 +743,7 @@ </span><span class="kw">use </span>juicebox_asm::insn::<span class="kw-2">*</span>; <span class="kw">use </span>juicebox_asm::Runtime; -<span class="kw">use </span>juicebox_asm::{Asm, Imm16, Imm64, MemOp, Reg16, Reg64}; +<span class="kw">use </span>juicebox_asm::{Asm, Imm16, Imm64, Mem16, Reg16, Reg64}; <span class="doccomment">/// A guest physical address. </span><span class="kw">pub struct </span>PhysAddr(<span class="kw">pub </span>u16); @@ -990,11 +990,11 @@ // Generate memory operand into regs for guest register. </span><span class="kw">let </span>reg_op = |r: TinyReg| { - MemOp::IndirectDisp(Reg64::rdi, (r.idx() * <span class="number">2</span>).try_into().expect(<span class="string">"only 3 regs"</span>)) + Mem16::indirect_disp(Reg64::rdi, (r.idx() * <span class="number">2</span>).try_into().expect(<span class="string">"only 3 regs"</span>)) }; <span class="comment">// Generate memory operand into dmem for guest phys address. - </span><span class="kw">let </span>mem_op = |paddr: u16| MemOp::IndirectDisp(Reg64::rsi, paddr.into()); + </span><span class="kw">let </span>mem_op = |paddr: u16| Mem16::indirect_disp(Reg64::rsi, paddr.into()); <span class="comment">// Compute instructions in translated basic block. </span><span class="kw">let </span>bb_icnt = || -> u64 { (pc - <span class="self">self</span>.pc).try_into().unwrap() }; |