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-rw-r--r--src/insn.rs16
-rw-r--r--src/insn/cmovnz.rs8
-rw-r--r--src/insn/cmovz.rs8
3 files changed, 32 insertions, 0 deletions
diff --git a/src/insn.rs b/src/insn.rs
index 60004d2..c02206c 100644
--- a/src/insn.rs
+++ b/src/insn.rs
@@ -2,6 +2,8 @@
mod add;
mod call;
+mod cmovnz;
+mod cmovz;
mod cmp;
mod dec;
mod jmp;
@@ -26,6 +28,20 @@ pub trait Call<T> {
fn call(&mut self, op1: T);
}
+pub trait Cmovnz<T, U> {
+ /// Emit a (conditional) move if not zero instruction.
+ ///
+ /// Move is only commited if (ZF=0).
+ fn cmovnz(&mut self, op1: T, op2: U);
+}
+
+pub trait Cmovz<T, U> {
+ /// Emit a (conditional) move if zero instruction.
+ ///
+ /// Move is only commited if (ZF=1).
+ fn cmovz(&mut self, op1: T, op2: U);
+}
+
/// Trait for [`cmp`](https://www.felixcloutier.com/x86/cmp) instruction kinds.
pub trait Cmp<T, U> {
/// Emit a compare instruction.
diff --git a/src/insn/cmovnz.rs b/src/insn/cmovnz.rs
new file mode 100644
index 0000000..3e7f21c
--- /dev/null
+++ b/src/insn/cmovnz.rs
@@ -0,0 +1,8 @@
+use super::Cmovnz;
+use crate::{Asm, Reg64};
+
+impl Cmovnz<Reg64, Reg64> for Asm {
+ fn cmovnz(&mut self, op1: Reg64, op2: Reg64) {
+ self.encode_rr(&[0x0f, 0x45], op2, op1);
+ }
+}
diff --git a/src/insn/cmovz.rs b/src/insn/cmovz.rs
new file mode 100644
index 0000000..c49aa35
--- /dev/null
+++ b/src/insn/cmovz.rs
@@ -0,0 +1,8 @@
+use super::Cmovz;
+use crate::{Asm, Reg64};
+
+impl Cmovz<Reg64, Reg64> for Asm {
+ fn cmovz(&mut self, op1: Reg64, op2: Reg64) {
+ self.encode_rr(&[0x0f, 0x44], op2, op1);
+ }
+}