From efd6fd88d2c73ae48ff74ba9e772e2347009fe9e Mon Sep 17 00:00:00 2001 From: johannst Date: Fri, 13 Dec 2024 21:12:22 +0000 Subject: deploy: e6095b086f6e2429fb952ae75a193dc89b4b9082 --- bf/index.html | 2 +- juicebox_asm/enum.Reg64.html | 4 +- juicebox_asm/insn/trait.Cmp.html | 2 +- juicebox_asm/struct.Asm.html | 4 +- search-index.js | 4 +- src/bf/bf.rs.html | 184 ++++++++++++++++++++++++++++++++------ src/fib/fib.rs.html | 2 +- src/juicebox_asm/insn/cmp.rs.html | 16 +++- 8 files changed, 180 insertions(+), 38 deletions(-) diff --git a/bf/index.html b/bf/index.html index ead5e8f..c79704e 100644 --- a/bf/index.html +++ b/bf/index.html @@ -1,4 +1,4 @@ -bf - Rust

Crate bf

source
Expand description

Brainfuck VM.

+bf - Rust

Crate bf

source
Expand description

Brainfuck VM.

This example implements a simple brainfuck interpreter [BrainfuckInterp] and a jit compiler [BrainfuckJit].

diff --git a/juicebox_asm/enum.Reg64.html b/juicebox_asm/enum.Reg64.html index 4ea005a..d63dddd 100644 --- a/juicebox_asm/enum.Reg64.html +++ b/juicebox_asm/enum.Reg64.html @@ -1,4 +1,4 @@ -Reg64 in juicebox_asm - Rust
juicebox_asm

Enum Reg64

source
#[repr(u8)]
pub enum Reg64 { +Reg64 in juicebox_asm - Rust
juicebox_asm

Enum Reg64

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#[repr(u8)]
pub enum Reg64 {
Show 16 variants rax = 0, rcx = 1, rdx = 2, @@ -16,7 +16,7 @@ r14 = 14, r15 = 15,
}
Expand description

Definition of 64 bit registers.

-

Variants§

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rax = 0

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rcx = 1

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rdx = 2

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rbx = 3

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rsp = 4

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rbp = 5

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rsi = 6

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rdi = 7

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r8 = 8

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r9 = 9

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r10 = 10

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r11 = 11

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r12 = 12

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r13 = 13

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r14 = 14

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r15 = 15

Trait Implementations§

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impl Add<Mem64, Reg64> for Asm

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fn add(&mut self, op1: Mem64, op2: Reg64)

Emit an add instruction.
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impl Add<Reg64, Mem64> for Asm

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fn add(&mut self, op1: Reg64, op2: Mem64)

Emit an add instruction.
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impl Add<Reg64, Reg64> for Asm

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fn add(&mut self, op1: Reg64, op2: Reg64)

Emit an add instruction.
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impl Call<Reg64> for Asm

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fn call(&mut self, op1: Reg64)

Emit a call instruction.
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impl Clone for Reg64

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fn clone(&self) -> Reg64

Returns a copy of the value. Read more
1.0.0 · source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
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impl Cmovnz<Reg64, Reg64> for Asm

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fn cmovnz(&mut self, op1: Reg64, op2: Reg64)

Emit a (conditional) move if not zero instruction. Read more
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impl Cmovz<Reg64, Reg64> for Asm

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fn cmovz(&mut self, op1: Reg64, op2: Reg64)

Emit a (conditional) move if zero instruction. Read more
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impl Dec<Reg64> for Asm

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fn dec(&mut self, op1: Reg64)

Emit a decrement instruction.
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impl Inc<Reg64> for Asm

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fn inc(&mut self, op1: Reg64)

Emit a increment instruction.
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impl Mov<Mem64, Reg64> for Asm

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fn mov(&mut self, op1: Mem64, op2: Reg64)

Emit an move instruction.
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impl Mov<Reg64, Imm64> for Asm

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fn mov(&mut self, op1: Reg64, op2: Imm64)

Emit an move instruction.
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impl Mov<Reg64, Mem64> for Asm

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fn mov(&mut self, op1: Reg64, op2: Mem64)

Emit an move instruction.
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impl Mov<Reg64, Reg64> for Asm

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fn mov(&mut self, op1: Reg64, op2: Reg64)

Emit an move instruction.
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impl Pop<Reg64> for Asm

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fn pop(&mut self, op1: Reg64)

Emit a pop instruction.
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impl Push<Reg64> for Asm

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fn push(&mut self, op1: Reg64)

Emit a push instruction.
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impl Sub<Reg64, Reg64> for Asm

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fn sub(&mut self, op1: Reg64, op2: Reg64)

Emit an sub instruction.
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impl Test<Reg64, Reg64> for Asm

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fn test(&mut self, op1: Reg64, op2: Reg64)

Emit a logical compare instruction. Read more
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impl Xor<Reg64, Reg64> for Asm

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fn xor(&mut self, op1: Reg64, op2: Reg64)

Emit a xor instruction.
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impl Copy for Reg64

Auto Trait Implementations§

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impl Freeze for Reg64

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impl RefUnwindSafe for Reg64

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impl Send for Reg64

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impl Sync for Reg64

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impl Unpin for Reg64

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impl UnwindSafe for Reg64

Blanket Implementations§

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impl<T> Any for T
where +

Variants§

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rax = 0

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rcx = 1

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rdx = 2

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rbx = 3

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rsp = 4

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rbp = 5

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rsi = 6

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rdi = 7

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r8 = 8

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r9 = 9

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r10 = 10

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r11 = 11

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r12 = 12

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r13 = 13

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r14 = 14

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r15 = 15

Trait Implementations§

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impl Add<Mem64, Reg64> for Asm

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fn add(&mut self, op1: Mem64, op2: Reg64)

Emit an add instruction.
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impl Add<Reg64, Mem64> for Asm

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fn add(&mut self, op1: Reg64, op2: Mem64)

Emit an add instruction.
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impl Add<Reg64, Reg64> for Asm

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fn add(&mut self, op1: Reg64, op2: Reg64)

Emit an add instruction.
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impl Call<Reg64> for Asm

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fn call(&mut self, op1: Reg64)

Emit a call instruction.
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impl Clone for Reg64

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fn clone(&self) -> Reg64

Returns a copy of the value. Read more
1.0.0 · source§

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source. Read more
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impl Cmovnz<Reg64, Reg64> for Asm

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fn cmovnz(&mut self, op1: Reg64, op2: Reg64)

Emit a (conditional) move if not zero instruction. Read more
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impl Cmovz<Reg64, Reg64> for Asm

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fn cmovz(&mut self, op1: Reg64, op2: Reg64)

Emit a (conditional) move if zero instruction. Read more
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impl Cmp<Reg64, Reg64> for Asm

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fn cmp(&mut self, op1: Reg64, op2: Reg64)

Emit a compare instruction. Read more
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impl Dec<Reg64> for Asm

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fn dec(&mut self, op1: Reg64)

Emit a decrement instruction.
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impl Inc<Reg64> for Asm

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fn inc(&mut self, op1: Reg64)

Emit a increment instruction.
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impl Mov<Mem64, Reg64> for Asm

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fn mov(&mut self, op1: Mem64, op2: Reg64)

Emit an move instruction.
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impl Mov<Reg64, Imm64> for Asm

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fn mov(&mut self, op1: Reg64, op2: Imm64)

Emit an move instruction.
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impl Mov<Reg64, Mem64> for Asm

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fn mov(&mut self, op1: Reg64, op2: Mem64)

Emit an move instruction.
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impl Mov<Reg64, Reg64> for Asm

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fn mov(&mut self, op1: Reg64, op2: Reg64)

Emit an move instruction.
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impl Pop<Reg64> for Asm

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fn pop(&mut self, op1: Reg64)

Emit a pop instruction.
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impl Push<Reg64> for Asm

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fn push(&mut self, op1: Reg64)

Emit a push instruction.
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impl Sub<Reg64, Reg64> for Asm

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fn sub(&mut self, op1: Reg64, op2: Reg64)

Emit an sub instruction.
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impl Test<Reg64, Reg64> for Asm

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fn test(&mut self, op1: Reg64, op2: Reg64)

Emit a logical compare instruction. Read more
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impl Xor<Reg64, Reg64> for Asm

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fn xor(&mut self, op1: Reg64, op2: Reg64)

Emit a xor instruction.
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impl Copy for Reg64

Auto Trait Implementations§

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impl Freeze for Reg64

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impl RefUnwindSafe for Reg64

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impl Send for Reg64

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impl Sync for Reg64

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impl Unpin for Reg64

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impl UnwindSafe for Reg64

Blanket Implementations§

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> CloneToUninit for T
where diff --git a/juicebox_asm/insn/trait.Cmp.html b/juicebox_asm/insn/trait.Cmp.html index 46fd3d6..20289b5 100644 --- a/juicebox_asm/insn/trait.Cmp.html +++ b/juicebox_asm/insn/trait.Cmp.html @@ -5,4 +5,4 @@

Required Methods§

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fn cmp(&mut self, op1: T, op2: U)

Emit a compare instruction.

Computes op2 - op1 and sets the status flags in the same way as the sub instruction, the result is discarded.

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Implementors§

\ No newline at end of file +

Implementors§

\ No newline at end of file diff --git a/juicebox_asm/struct.Asm.html b/juicebox_asm/struct.Asm.html index 0991a04..19579f8 100644 --- a/juicebox_asm/struct.Asm.html +++ b/juicebox_asm/struct.Asm.html @@ -1,10 +1,10 @@ -Asm in juicebox_asm - Rust
juicebox_asm

Struct Asm

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pub struct Asm { /* private fields */ }
Expand description

x64 jit assembler.

+Asm in juicebox_asm - Rust
juicebox_asm

Struct Asm

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pub struct Asm { /* private fields */ }
Expand description

x64 jit assembler.

Implementations§

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impl Asm

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pub fn new() -> Asm

Create a new x64 jit assembler.

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pub fn into_code(self) -> Vec<u8>

Consume the assembler and get the emitted code.

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pub fn bind(&mut self, label: &mut Label)

Bind the Label to the current location.

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impl Asm

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pub fn nop(&mut self)

Emit a nop instruction.

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impl Asm

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pub fn ret(&mut self)

Emit a ret instruction.

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Trait Implementations§

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impl Add<Mem16, Imm16> for Asm

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fn add(&mut self, op1: Mem16, op2: Imm16)

Emit an add instruction.
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impl Add<Mem16, Imm8> for Asm

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fn add(&mut self, op1: Mem16, op2: Imm8)

Emit an add instruction.
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impl Add<Mem16, Reg16> for Asm

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fn add(&mut self, op1: Mem16, op2: Reg16)

Emit an add instruction.
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impl Add<Mem32, Imm8> for Asm

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fn add(&mut self, op1: Mem32, op2: Imm8)

Emit an add instruction.
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impl Add<Mem64, Imm8> for Asm

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fn add(&mut self, op1: Mem64, op2: Imm8)

Emit an add instruction.
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impl Add<Mem64, Reg64> for Asm

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fn add(&mut self, op1: Mem64, op2: Reg64)

Emit an add instruction.
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impl Add<Mem8, Imm8> for Asm

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fn add(&mut self, op1: Mem8, op2: Imm8)

Emit an add instruction.
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impl Add<Reg32, Reg32> for Asm

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fn add(&mut self, op1: Reg32, op2: Reg32)

Emit an add instruction.
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impl Add<Reg64, Mem64> for Asm

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fn add(&mut self, op1: Reg64, op2: Mem64)

Emit an add instruction.
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impl Add<Reg64, Reg64> for Asm

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fn add(&mut self, op1: Reg64, op2: Reg64)

Emit an add instruction.
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impl Call<Reg64> for Asm

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fn call(&mut self, op1: Reg64)

Emit a call instruction.
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impl Cmovnz<Reg64, Reg64> for Asm

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fn cmovnz(&mut self, op1: Reg64, op2: Reg64)

Emit a (conditional) move if not zero instruction. Read more
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impl Cmovz<Reg64, Reg64> for Asm

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fn cmovz(&mut self, op1: Reg64, op2: Reg64)

Emit a (conditional) move if zero instruction. Read more
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impl Cmp<Mem16, Imm16> for Asm

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fn cmp(&mut self, op1: Mem16, op2: Imm16)

Emit a compare instruction. Read more
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impl Cmp<Mem8, Imm8> for Asm

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fn cmp(&mut self, op1: Mem8, op2: Imm8)

Emit a compare instruction. Read more
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impl Dec<Mem16> for Asm

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fn dec(&mut self, op1: Mem16)

Emit a decrement instruction.
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impl Dec<Mem32> for Asm

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fn dec(&mut self, op1: Mem32)

Emit a decrement instruction.
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impl Dec<Mem64> for Asm

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fn dec(&mut self, op1: Mem64)

Emit a decrement instruction.
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impl Dec<Mem8> for Asm

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fn dec(&mut self, op1: Mem8)

Emit a decrement instruction.
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impl Dec<Reg32> for Asm

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fn dec(&mut self, op1: Reg32)

Emit a decrement instruction.
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impl Dec<Reg64> for Asm

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fn dec(&mut self, op1: Reg64)

Emit a decrement instruction.
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impl Inc<Mem16> for Asm

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fn inc(&mut self, op1: Mem16)

Emit a increment instruction.
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impl Inc<Mem32> for Asm

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fn inc(&mut self, op1: Mem32)

Emit a increment instruction.
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impl Inc<Mem64> for Asm

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fn inc(&mut self, op1: Mem64)

Emit a increment instruction.
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impl Inc<Mem8> for Asm

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fn inc(&mut self, op1: Mem8)

Emit a increment instruction.
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impl Inc<Reg32> for Asm

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fn inc(&mut self, op1: Reg32)

Emit a increment instruction.
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impl Inc<Reg64> for Asm

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fn inc(&mut self, op1: Reg64)

Emit a increment instruction.
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impl Jmp<&mut Label> for Asm

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fn jmp(&mut self, op1: &mut Label)

Emit an unconditional jump instruction.
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impl Jnz<&mut Label> for Asm

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fn jnz(&mut self, op1: &mut Label)

Emit a conditional jump if not zero instruction (ZF = 0).
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impl Jz<&mut Label> for Asm

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fn jz(&mut self, op1: &mut Label)

Emit a conditional jump if zero instruction (ZF = 1).
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impl Mov<Mem16, Imm16> for Asm

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fn mov(&mut self, op1: Mem16, op2: Imm16)

Emit an move instruction.
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impl Mov<Mem16, Reg16> for Asm

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fn mov(&mut self, op1: Mem16, op2: Reg16)

Emit an move instruction.
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impl Mov<Mem32, Reg32> for Asm

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fn mov(&mut self, op1: Mem32, op2: Reg32)

Emit an move instruction.
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impl Mov<Mem64, Reg64> for Asm

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fn mov(&mut self, op1: Mem64, op2: Reg64)

Emit an move instruction.
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impl Mov<Mem8, Reg8> for Asm

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fn mov(&mut self, op1: Mem8, op2: Reg8)

Emit an move instruction.
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impl Mov<Reg16, Imm16> for Asm

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fn mov(&mut self, op1: Reg16, op2: Imm16)

Emit an move instruction.
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impl Mov<Reg16, Mem16> for Asm

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fn mov(&mut self, op1: Reg16, op2: Mem16)

Emit an move instruction.
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impl Mov<Reg16, Reg16> for Asm

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fn mov(&mut self, op1: Reg16, op2: Reg16)

Emit an move instruction.
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impl Mov<Reg32, Imm32> for Asm

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fn mov(&mut self, op1: Reg32, op2: Imm32)

Emit an move instruction.
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impl Mov<Reg32, Mem32> for Asm

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fn mov(&mut self, op1: Reg32, op2: Mem32)

Emit an move instruction.
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impl Mov<Reg32, Reg32> for Asm

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fn mov(&mut self, op1: Reg32, op2: Reg32)

Emit an move instruction.
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impl Mov<Reg64, Imm64> for Asm

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fn mov(&mut self, op1: Reg64, op2: Imm64)

Emit an move instruction.
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impl Mov<Reg64, Mem64> for Asm

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fn mov(&mut self, op1: Reg64, op2: Mem64)

Emit an move instruction.
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impl Mov<Reg64, Reg64> for Asm

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fn mov(&mut self, op1: Reg64, op2: Reg64)

Emit an move instruction.
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impl Mov<Reg8, Imm8> for Asm

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fn mov(&mut self, op1: Reg8, op2: Imm8)

Emit an move instruction.
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impl Mov<Reg8, Mem8> for Asm

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fn mov(&mut self, op1: Reg8, op2: Mem8)

Emit an move instruction.
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impl Mov<Reg8, Reg8> for Asm

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fn mov(&mut self, op1: Reg8, op2: Reg8)

Emit an move instruction.
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impl Pop<Reg16> for Asm

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fn pop(&mut self, op1: Reg16)

Emit a pop instruction.
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impl Pop<Reg64> for Asm

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fn pop(&mut self, op1: Reg64)

Emit a pop instruction.
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impl Push<Reg16> for Asm

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fn push(&mut self, op1: Reg16)

Emit a push instruction.
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impl Push<Reg64> for Asm

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fn push(&mut self, op1: Reg64)

Emit a push instruction.
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impl Sub<Mem8, Imm8> for Asm

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fn sub(&mut self, op1: Mem8, op2: Imm8)

Emit an sub instruction.
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impl Sub<Reg64, Reg64> for Asm

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fn sub(&mut self, op1: Reg64, op2: Reg64)

Emit an sub instruction.
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impl Test<Mem16, Imm16> for Asm

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fn test(&mut self, op1: Mem16, op2: Imm16)

Emit a logical compare instruction. Read more
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impl Test<Reg32, Reg32> for Asm

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fn test(&mut self, op1: Reg32, op2: Reg32)

Emit a logical compare instruction. Read more
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impl Test<Reg64, Reg64> for Asm

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fn test(&mut self, op1: Reg64, op2: Reg64)

Emit a logical compare instruction. Read more
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impl Xor<Reg64, Reg64> for Asm

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fn xor(&mut self, op1: Reg64, op2: Reg64)

Emit a xor instruction.

Auto Trait Implementations§

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impl Freeze for Asm

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impl RefUnwindSafe for Asm

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impl Send for Asm

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impl Sync for Asm

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impl Unpin for Asm

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impl UnwindSafe for Asm

Blanket Implementations§

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impl<T> Any for T
where +

Trait Implementations§

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impl Add<Mem16, Imm16> for Asm

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fn add(&mut self, op1: Mem16, op2: Imm16)

Emit an add instruction.
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impl Add<Mem16, Imm8> for Asm

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fn add(&mut self, op1: Mem16, op2: Imm8)

Emit an add instruction.
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impl Add<Mem16, Reg16> for Asm

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fn add(&mut self, op1: Mem16, op2: Reg16)

Emit an add instruction.
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impl Add<Mem32, Imm8> for Asm

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fn add(&mut self, op1: Mem32, op2: Imm8)

Emit an add instruction.
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impl Add<Mem64, Imm8> for Asm

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fn add(&mut self, op1: Mem64, op2: Imm8)

Emit an add instruction.
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impl Add<Mem64, Reg64> for Asm

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fn add(&mut self, op1: Mem64, op2: Reg64)

Emit an add instruction.
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impl Add<Mem8, Imm8> for Asm

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fn add(&mut self, op1: Mem8, op2: Imm8)

Emit an add instruction.
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impl Add<Reg32, Reg32> for Asm

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fn add(&mut self, op1: Reg32, op2: Reg32)

Emit an add instruction.
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impl Add<Reg64, Mem64> for Asm

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fn add(&mut self, op1: Reg64, op2: Mem64)

Emit an add instruction.
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impl Add<Reg64, Reg64> for Asm

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fn add(&mut self, op1: Reg64, op2: Reg64)

Emit an add instruction.
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impl Call<Reg64> for Asm

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fn call(&mut self, op1: Reg64)

Emit a call instruction.
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impl Cmovnz<Reg64, Reg64> for Asm

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fn cmovnz(&mut self, op1: Reg64, op2: Reg64)

Emit a (conditional) move if not zero instruction. Read more
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impl Cmovz<Reg64, Reg64> for Asm

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fn cmovz(&mut self, op1: Reg64, op2: Reg64)

Emit a (conditional) move if zero instruction. Read more
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impl Cmp<Mem16, Imm16> for Asm

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fn cmp(&mut self, op1: Mem16, op2: Imm16)

Emit a compare instruction. Read more
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impl Cmp<Mem8, Imm8> for Asm

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fn cmp(&mut self, op1: Mem8, op2: Imm8)

Emit a compare instruction. Read more
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impl Cmp<Reg64, Reg64> for Asm

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fn cmp(&mut self, op1: Reg64, op2: Reg64)

Emit a compare instruction. Read more
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impl Dec<Mem16> for Asm

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fn dec(&mut self, op1: Mem16)

Emit a decrement instruction.
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impl Dec<Mem32> for Asm

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fn dec(&mut self, op1: Mem32)

Emit a decrement instruction.
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impl Dec<Mem64> for Asm

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fn dec(&mut self, op1: Mem64)

Emit a decrement instruction.
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impl Dec<Mem8> for Asm

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fn dec(&mut self, op1: Mem8)

Emit a decrement instruction.
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impl Dec<Reg32> for Asm

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fn dec(&mut self, op1: Reg32)

Emit a decrement instruction.
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impl Dec<Reg64> for Asm

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fn dec(&mut self, op1: Reg64)

Emit a decrement instruction.
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impl Inc<Mem16> for Asm

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fn inc(&mut self, op1: Mem16)

Emit a increment instruction.
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impl Inc<Mem32> for Asm

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fn inc(&mut self, op1: Mem32)

Emit a increment instruction.
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impl Inc<Mem64> for Asm

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fn inc(&mut self, op1: Mem64)

Emit a increment instruction.
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impl Inc<Mem8> for Asm

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fn inc(&mut self, op1: Mem8)

Emit a increment instruction.
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impl Inc<Reg32> for Asm

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fn inc(&mut self, op1: Reg32)

Emit a increment instruction.
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impl Inc<Reg64> for Asm

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fn inc(&mut self, op1: Reg64)

Emit a increment instruction.
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impl Jmp<&mut Label> for Asm

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fn jmp(&mut self, op1: &mut Label)

Emit an unconditional jump instruction.
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impl Jnz<&mut Label> for Asm

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fn jnz(&mut self, op1: &mut Label)

Emit a conditional jump if not zero instruction (ZF = 0).
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impl Jz<&mut Label> for Asm

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fn jz(&mut self, op1: &mut Label)

Emit a conditional jump if zero instruction (ZF = 1).
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impl Mov<Mem16, Imm16> for Asm

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fn mov(&mut self, op1: Mem16, op2: Imm16)

Emit an move instruction.
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impl Mov<Mem16, Reg16> for Asm

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fn mov(&mut self, op1: Mem16, op2: Reg16)

Emit an move instruction.
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impl Mov<Mem32, Reg32> for Asm

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fn mov(&mut self, op1: Mem32, op2: Reg32)

Emit an move instruction.
source§

impl Mov<Mem64, Reg64> for Asm

source§

fn mov(&mut self, op1: Mem64, op2: Reg64)

Emit an move instruction.
source§

impl Mov<Mem8, Reg8> for Asm

source§

fn mov(&mut self, op1: Mem8, op2: Reg8)

Emit an move instruction.
source§

impl Mov<Reg16, Imm16> for Asm

source§

fn mov(&mut self, op1: Reg16, op2: Imm16)

Emit an move instruction.
source§

impl Mov<Reg16, Mem16> for Asm

source§

fn mov(&mut self, op1: Reg16, op2: Mem16)

Emit an move instruction.
source§

impl Mov<Reg16, Reg16> for Asm

source§

fn mov(&mut self, op1: Reg16, op2: Reg16)

Emit an move instruction.
source§

impl Mov<Reg32, Imm32> for Asm

source§

fn mov(&mut self, op1: Reg32, op2: Imm32)

Emit an move instruction.
source§

impl Mov<Reg32, Mem32> for Asm

source§

fn mov(&mut self, op1: Reg32, op2: Mem32)

Emit an move instruction.
source§

impl Mov<Reg32, Reg32> for Asm

source§

fn mov(&mut self, op1: Reg32, op2: Reg32)

Emit an move instruction.
source§

impl Mov<Reg64, Imm64> for Asm

source§

fn mov(&mut self, op1: Reg64, op2: Imm64)

Emit an move instruction.
source§

impl Mov<Reg64, Mem64> for Asm

source§

fn mov(&mut self, op1: Reg64, op2: Mem64)

Emit an move instruction.
source§

impl Mov<Reg64, Reg64> for Asm

source§

fn mov(&mut self, op1: Reg64, op2: Reg64)

Emit an move instruction.
source§

impl Mov<Reg8, Imm8> for Asm

source§

fn mov(&mut self, op1: Reg8, op2: Imm8)

Emit an move instruction.
source§

impl Mov<Reg8, Mem8> for Asm

source§

fn mov(&mut self, op1: Reg8, op2: Mem8)

Emit an move instruction.
source§

impl Mov<Reg8, Reg8> for Asm

source§

fn mov(&mut self, op1: Reg8, op2: Reg8)

Emit an move instruction.
source§

impl Pop<Reg16> for Asm

source§

fn pop(&mut self, op1: Reg16)

Emit a pop instruction.
source§

impl Pop<Reg64> for Asm

source§

fn pop(&mut self, op1: Reg64)

Emit a pop instruction.
source§

impl Push<Reg16> for Asm

source§

fn push(&mut self, op1: Reg16)

Emit a push instruction.
source§

impl Push<Reg64> for Asm

source§

fn push(&mut self, op1: Reg64)

Emit a push instruction.
source§

impl Sub<Mem8, Imm8> for Asm

source§

fn sub(&mut self, op1: Mem8, op2: Imm8)

Emit an sub instruction.
source§

impl Sub<Reg64, Reg64> for Asm

source§

fn sub(&mut self, op1: Reg64, op2: Reg64)

Emit an sub instruction.
source§

impl Test<Mem16, Imm16> for Asm

source§

fn test(&mut self, op1: Mem16, op2: Imm16)

Emit a logical compare instruction. Read more
source§

impl Test<Reg32, Reg32> for Asm

source§

fn test(&mut self, op1: Reg32, op2: Reg32)

Emit a logical compare instruction. Read more
source§

impl Test<Reg64, Reg64> for Asm

source§

fn test(&mut self, op1: Reg64, op2: Reg64)

Emit a logical compare instruction. Read more
source§

impl Xor<Reg64, Reg64> for Asm

source§

fn xor(&mut self, op1: Reg64, op2: Reg64)

Emit a xor instruction.

Auto Trait Implementations§

§

impl Freeze for Asm

§

impl RefUnwindSafe for Asm

§

impl Send for Asm

§

impl Sync for Asm

§

impl Unpin for Asm

§

impl UnwindSafe for Asm

Blanket Implementations§

source§

impl<T> Any for T
where T: 'static + ?Sized,

source§

fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
source§

impl<T> Borrow<T> for T
where T: ?Sized,

source§

fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
source§

impl<T> BorrowMut<T> for T
where T: ?Sized,

source§

fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
source§

impl<T> From<T> for T

source§

fn from(t: T) -> T

Returns the argument unchanged.

diff --git a/search-index.js b/search-index.js index e3b63f0..293232d 100644 --- a/search-index.js +++ b/search-index.js @@ -1,4 +1,4 @@ -var searchIndex = new Map(JSON.parse('[["add",{"t":"","n":[],"q":[],"i":"","f":"","D":"b","p":[],"r":[],"b":[],"c":"OjAAAAAAAAA=","e":"OjAAAAAAAAA="}],["bf",{"t":"","n":[],"q":[],"i":"","f":"","D":"b","p":[],"r":[],"b":[],"c":"OjAAAAAAAAA=","e":"OjAAAAAAAAA="}],["fib",{"t":"","n":[],"q":[],"i":"","f":"","D":"b","p":[],"r":[],"b":[],"c":"OjAAAAAAAAA=","e":"OjAAAAAAAAA="}],["juicebox_asm",{"t":"FFFFFFFFFFGGGGFNNNNNNNNNNNPPPPNPNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNPPPNPPNNNNNNNNNNNNNNNNPNNNNNNPPPPNNNPPPPPPPPPNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNCNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPNPPPPPPNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNKKKKKKKKKKKKKKKKMMMMMMMMMMMMMMMM","n":["Asm","Imm16","Imm32","Imm64","Imm8","Label","Mem16","Mem32","Mem64","Mem8","Reg16","Reg32","Reg64","Reg8","Runtime","add","","","","","","","","","","add_code","ah","al","ax","bh","bind","bl","borrow","","","","","","","","","","","","","","","borrow_mut","","","","","","","","","","","","","","","bp","bpl","bx","call","ch","cl","clone","","","","clone_into","","","","clone_to_uninit","","","","cmovnz","cmovz","cmp","","cx","dec","","","","","","dh","di","dil","dl","drop","","dump","dx","eax","ebp","ebx","ecx","edi","edx","esi","esp","from","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","inc","","","","","","indirect","","","","indirect_base_index","","","","indirect_disp","","","","insn","into","","","","","","","","","","","","","","","into_code","jmp","jnz","jz","mov","","","","","","","","","","","","","","","","","new","","","nop","pop","","push","","r10","r10d","r10l","r10w","r11","r11d","r11l","r11w","r12","r12d","r12l","r12w","r13","r13d","r13l","r13w","r14","r14d","r14l","r14w","r15","r15d","r15l","r15w","r8","r8d","r8l","r8w","r9","r9d","r9l","r9w","rax","rbp","rbx","rcx","rdi","rdx","ret","rsi","rsp","si","sil","sp","spl","sub","","test","","","to_owned","","","","try_from","","","","","","","","","","","","","","","try_into","","","","","","","","","","","","","","","type_id","","","","","","","","","","","","","","","with_profile","xor","Add","Call","Cmovnz","Cmovz","Cmp","Dec","Inc","Jmp","Jnz","Jz","Mov","Pop","Push","Sub","Test","Xor","add","call","cmovnz","cmovz","cmp","dec","inc","jmp","jnz","jz","mov","pop","push","sub","test","xor"],"q":[[0,"juicebox_asm"],[308,"juicebox_asm::insn"],[340,"juicebox_asm::asm"],[341,"juicebox_asm::mem"],[342,"juicebox_asm::reg"],[343,"juicebox_asm::imm"],[344,"juicebox_asm::rt"],[345,"core::convert"],[346,"juicebox_asm::label"],[347,"alloc::vec"],[348,"core::result"],[349,"core::any"]],"i":"```````````````d000000000AlBf0Af1313Bd3A`AjBnCdnAbAdhjAh;<>:=9876543210;<;<;><<10;<10;<10;<>>>>;>>>>>><;<<:==;00000000>:=99988888777777766666666666543210;<>>>>>>543254325432`>:=9876543210;<>>>>>>>>>>>>>>>>>>>>>>:=>>>>>10<;10<;10<;10<;10<;10<;10<;10<;111111>11;<;<>>>>>10;<>:=9876543210;<>:=9876543210;<>:=9876543210;<=>````````````````DdDfDhDjDlDnE`EbEdEfEhEjElEnF`Fb","f":"```````````````{{{f{bd}}hj}l}{{{f{bd}}jh}l}{{{f{bd}}nA`}l}{{{f{bd}}AbA`}l}{{{f{bd}}AdA`}l}{{{f{bd}}AbAf}l}{{{f{bd}}hA`}l}{{{f{bd}}jj}l}{{{f{bd}}AhAh}l}{{{f{bd}}AbAj}l}{{{f{bAl}}c}e{{Bb{{B`{An}}}}}{}}````{{{f{bd}}{f{bBd}}}l}`{f{{f{c}}}{}}00000000000000{{{f{b}}}{{f{bc}}}{}}00000000000000```{{{f{bd}}j}l}``{{{f{j}}}j}{{{f{Ah}}}Ah}{{{f{Af}}}Af}{{{f{Bf}}}Bf}{{f{f{bc}}}l{}}000{fl}000==;{{{f{bd}}nA`}l}`{{{f{bd}}h}l}8{{{f{bd}}Ah}l}{{{f{bd}}Ad}l}{{{f{bd}}n}l}{{{f{bd}}Ab}l}````{{{f{bBd}}}l}{{{f{bAl}}}l}{{{f{Al}}}l}`````````{cc{}}000{AnA`}{BhA`}{BjAj}{BlAj}{BhAj}5{AnAj}{BjBn}{AnBn}8{C`Bn}{BhBn}{CbBn}{BlBn}{BhCd}{CfCd}{ChCd}{CjCd}{C`Cd}{CbCd}{BlCd}{ClCd}{BjCd}{AnCd}{cc{}}00000000{{{f{bd}}Ad}l}{{{f{bd}}h}l}{{{f{bd}}Ab}l}{{{f{bd}}n}l}{{{f{bd}}Ah}l}{{{f{bd}}j}l}{jn}{jAb}{jAd}{jh}{{jj}n}{{jj}Ab}{{jj}Ad}{{jj}h}{{jCb}n}{{jCb}Ab}{{jCb}Ad}{{jCb}h}`{{}c{}}00000000000000{d{{Cn{An}}}}{{{f{bd}}{f{bBd}}}l}00{{{f{bd}}AfAj}l}{{{f{bd}}AhAh}l}{{{f{bd}}AbAf}l}{{{f{bd}}AdAh}l}{{{f{bd}}nBf}l}{{{f{bd}}jj}l}{{{f{bd}}hj}l}{{{f{bd}}BfBf}l}{{{f{bd}}jh}l}{{{f{bd}}AbAj}l}{{{f{bd}}BfA`}l}{{{f{bd}}AhAd}l}{{{f{bd}}AfAb}l}{{{f{bd}}Bfn}l}{{{f{bd}}AfAf}l}{{{f{bd}}jCd}l}{{{f{bd}}AhBn}l}{{}d}{{}Bd}{{}Al}{{{f{bd}}}l}{{{f{bd}}j}l}{{{f{bd}}Af}l}01``````````````````````````````````````2``````{{{f{bd}}jj}l}{{{f{bd}}nA`}l}{{{f{bd}}AhAh}l}2{{{f{bd}}AbAj}l}{fc{}}000{c{{D`{e}}}{}{}}00000000000000{{}{{D`{c}}}{}}00000000000000{fDb}00000000000000;7````````````````{{{f{bDd}}ce}l{}{}}{{{f{bDf}}c}l{}}{{{f{bDh}}ce}l{}{}}{{{f{bDj}}ce}l{}{}}{{{f{bDl}}ce}l{}{}}{{{f{bDn}}c}l{}}{{{f{bE`}}c}l{}}{{{f{bEb}}c}l{}}{{{f{bEd}}c}l{}}{{{f{bEf}}c}l{}}{{{f{bEh}}ce}l{}{}}{{{f{bEj}}c}l{}}{{{f{bEl}}c}l{}}{{{f{bEn}}ce}l{}{}}{{{f{bF`}}ce}l{}{}}{{{f{bFb}}ce}l{}{}}","D":"Ll","p":[[0,"mut"],[5,"Asm",0,340],[1,"reference"],[5,"Mem64",0,341],[6,"Reg64",0,342],[1,"unit"],[5,"Mem8",0,341],[5,"Imm8",0,343],[5,"Mem16",0,341],[5,"Mem32",0,341],[6,"Reg16",0,342],[6,"Reg32",0,342],[5,"Imm16",0,343],[5,"Runtime",0,344],[1,"u8"],[1,"slice"],[10,"AsRef",345],[5,"Label",0,346],[6,"Reg8",0,342],[1,"i8"],[1,"i16"],[1,"u16"],[5,"Imm32",0,343],[1,"u32"],[1,"i32"],[5,"Imm64",0,343],[1,"usize"],[1,"u64"],[1,"i64"],[1,"isize"],[5,"Vec",347],[6,"Result",348],[5,"TypeId",349],[10,"Add",308],[10,"Call",308],[10,"Cmovnz",308],[10,"Cmovz",308],[10,"Cmp",308],[10,"Dec",308],[10,"Inc",308],[10,"Jmp",308],[10,"Jnz",308],[10,"Jz",308],[10,"Mov",308],[10,"Pop",308],[10,"Push",308],[10,"Sub",308],[10,"Test",308],[10,"Xor",308]],"r":[[0,340],[1,343],[2,343],[3,343],[4,343],[5,346],[6,341],[7,341],[8,341],[9,341],[10,342],[11,342],[12,342],[13,342],[14,344]],"b":[[15,"impl-Add%3CMem64,+Reg64%3E-for-Asm"],[16,"impl-Add%3CReg64,+Mem64%3E-for-Asm"],[17,"impl-Add%3CMem8,+Imm8%3E-for-Asm"],[18,"impl-Add%3CMem16,+Imm8%3E-for-Asm"],[19,"impl-Add%3CMem32,+Imm8%3E-for-Asm"],[20,"impl-Add%3CMem16,+Reg16%3E-for-Asm"],[21,"impl-Add%3CMem64,+Imm8%3E-for-Asm"],[22,"impl-Add%3CReg64,+Reg64%3E-for-Asm"],[23,"impl-Add%3CReg32,+Reg32%3E-for-Asm"],[24,"impl-Add%3CMem16,+Imm16%3E-for-Asm"],[82,"impl-Cmp%3CMem16,+Imm16%3E-for-Asm"],[83,"impl-Cmp%3CMem8,+Imm8%3E-for-Asm"],[85,"impl-Dec%3CMem64%3E-for-Asm"],[86,"impl-Dec%3CReg64%3E-for-Asm"],[87,"impl-Dec%3CReg32%3E-for-Asm"],[88,"impl-Dec%3CMem32%3E-for-Asm"],[89,"impl-Dec%3CMem8%3E-for-Asm"],[90,"impl-Dec%3CMem16%3E-for-Asm"],[111,"impl-From%3Cu8%3E-for-Imm8"],[112,"impl-From%3Ci8%3E-for-Imm8"],[113,"impl-From%3Ci16%3E-for-Imm16"],[114,"impl-From%3Cu16%3E-for-Imm16"],[115,"impl-From%3Ci8%3E-for-Imm16"],[117,"impl-From%3Cu8%3E-for-Imm16"],[118,"impl-From%3Ci16%3E-for-Imm32"],[119,"impl-From%3Cu8%3E-for-Imm32"],[121,"impl-From%3Cu32%3E-for-Imm32"],[122,"impl-From%3Ci8%3E-for-Imm32"],[123,"impl-From%3Ci32%3E-for-Imm32"],[124,"impl-From%3Cu16%3E-for-Imm32"],[125,"impl-From%3Ci8%3E-for-Imm64"],[126,"impl-From%3Cusize%3E-for-Imm64"],[127,"impl-From%3Cu64%3E-for-Imm64"],[128,"impl-From%3Ci64%3E-for-Imm64"],[129,"impl-From%3Cu32%3E-for-Imm64"],[130,"impl-From%3Ci32%3E-for-Imm64"],[131,"impl-From%3Cu16%3E-for-Imm64"],[132,"impl-From%3Cisize%3E-for-Imm64"],[133,"impl-From%3Ci16%3E-for-Imm64"],[134,"impl-From%3Cu8%3E-for-Imm64"],[144,"impl-Inc%3CMem32%3E-for-Asm"],[145,"impl-Inc%3CMem64%3E-for-Asm"],[146,"impl-Inc%3CMem16%3E-for-Asm"],[147,"impl-Inc%3CMem8%3E-for-Asm"],[148,"impl-Inc%3CReg32%3E-for-Asm"],[149,"impl-Inc%3CReg64%3E-for-Asm"],[182,"impl-Mov%3CReg16,+Imm16%3E-for-Asm"],[183,"impl-Mov%3CReg32,+Reg32%3E-for-Asm"],[184,"impl-Mov%3CMem16,+Reg16%3E-for-Asm"],[185,"impl-Mov%3CMem32,+Reg32%3E-for-Asm"],[186,"impl-Mov%3CMem8,+Reg8%3E-for-Asm"],[187,"impl-Mov%3CReg64,+Reg64%3E-for-Asm"],[188,"impl-Mov%3CMem64,+Reg64%3E-for-Asm"],[189,"impl-Mov%3CReg8,+Reg8%3E-for-Asm"],[190,"impl-Mov%3CReg64,+Mem64%3E-for-Asm"],[191,"impl-Mov%3CMem16,+Imm16%3E-for-Asm"],[192,"impl-Mov%3CReg8,+Imm8%3E-for-Asm"],[193,"impl-Mov%3CReg32,+Mem32%3E-for-Asm"],[194,"impl-Mov%3CReg16,+Mem16%3E-for-Asm"],[195,"impl-Mov%3CReg8,+Mem8%3E-for-Asm"],[196,"impl-Mov%3CReg16,+Reg16%3E-for-Asm"],[197,"impl-Mov%3CReg64,+Imm64%3E-for-Asm"],[198,"impl-Mov%3CReg32,+Imm32%3E-for-Asm"],[203,"impl-Pop%3CReg64%3E-for-Asm"],[204,"impl-Pop%3CReg16%3E-for-Asm"],[205,"impl-Push%3CReg16%3E-for-Asm"],[206,"impl-Push%3CReg64%3E-for-Asm"],[252,"impl-Sub%3CReg64,+Reg64%3E-for-Asm"],[253,"impl-Sub%3CMem8,+Imm8%3E-for-Asm"],[254,"impl-Test%3CReg32,+Reg32%3E-for-Asm"],[255,"impl-Test%3CReg64,+Reg64%3E-for-Asm"],[256,"impl-Test%3CMem16,+Imm16%3E-for-Asm"]],"c":"OjAAAAAAAAA=","e":"OzAAAAEAAO4ADAAQAAkAGwADACAAQABjAAgAcAAEAHYAAgB6AA0AkQAFALQAEwDMACkA9wA7ADQBAAA="}],["tiny_vm",{"t":"PPPPPPPFPPPFPGGFNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNHHHNNNNNNNNNNNNNNNNNNNNNNN","n":["A","Add","Addi","B","Branch","BranchZero","C","Fixup","Halt","Load","LoadImm","PhysAddr","Store","TinyInsn","TinyReg","TinyVm","bind","borrow","","","","","borrow_mut","","","","","clone","","clone_into","","clone_to_uninit","","dump","eq","","fmt","","from","","","","","interp","into","","","","","","jit","make_tinyvm_fib","make_tinyvm_jit_perf","make_tinyvm_jit_test","new","","read_mem","read_reg","to_owned","","try_from","","","","","try_into","","","","","type_id","","","","","write_mem","write_reg"],"q":[[0,"tiny_vm"],[77,"alloc::vec"],[78,"core::fmt"],[79,"core::result"],[80,"core::any"]],"i":"nf01001`000`0```bAhA`24310243434343043431024301102430```02004310243102431024300","f":"````````````````{{b{j{d{h{f}}}}}l}{j{{j{c}}}{}}0000{{{j{d}}}{{j{dc}}}{}}0000{{{j{n}}}n}{{{j{f}}}f}{{j{j{dc}}}l{}}0{jl}0{{{j{A`}}}l}{{{j{n}}{j{n}}}Ab}{{{j{f}}{j{f}}}Ab}{{{j{n}}{j{dAd}}}Af}{{{j{f}}{j{dAd}}}Af}{cc{}}0000{{{j{dA`}}}l}{AhAj}{{}c{}}00002{Al{{h{f}}}}{{}{{h{f}}}}0{{{h{f}}}A`}{Ajb}{{{j{A`}}Ah}Al}{{{j{A`}}n}Al}{jc{}}0{c{{An{e}}}{}{}}0000{{}{{An{c}}}{}}0000{jB`}0000{{{j{dA`}}AhAl}l}{{{j{dA`}}nAl}l}","D":"Dj","p":[[5,"Fixup",0],[0,"mut"],[6,"TinyInsn",0],[5,"Vec",77],[1,"reference"],[1,"unit"],[6,"TinyReg",0],[5,"TinyVm",0],[1,"bool"],[5,"Formatter",78],[8,"Result",78],[5,"PhysAddr",0],[1,"usize"],[1,"u16"],[6,"Result",79],[5,"TypeId",80]],"r":[],"b":[],"c":"OjAAAAAAAAA=","e":"OzAAAAEAACgABwABAAAABAAAAAcAAAASAA8AIwADAC0AAAA7ABAA"}]]')); +var searchIndex = new Map(JSON.parse('[["add",{"t":"","n":[],"q":[],"i":"","f":"","D":"b","p":[],"r":[],"b":[],"c":"OjAAAAAAAAA=","e":"OjAAAAAAAAA="}],["bf",{"t":"","n":[],"q":[],"i":"","f":"","D":"b","p":[],"r":[],"b":[],"c":"OjAAAAAAAAA=","e":"OjAAAAAAAAA="}],["fib",{"t":"","n":[],"q":[],"i":"","f":"","D":"b","p":[],"r":[],"b":[],"c":"OjAAAAAAAAA=","e":"OjAAAAAAAAA="}],["juicebox_asm",{"t":"FFFFFFFFFFGGGGFNNNNNNNNNNNPPPPNPNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNPPPNPPNNNNNNNNNNNNNNNNNPNNNNNNPPPPNNNPPPPPPPPPNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNCNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPPNPPPPPPNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNKKKKKKKKKKKKKKKKMMMMMMMMMMMMMMMM","n":["Asm","Imm16","Imm32","Imm64","Imm8","Label","Mem16","Mem32","Mem64","Mem8","Reg16","Reg32","Reg64","Reg8","Runtime","add","","","","","","","","","","add_code","ah","al","ax","bh","bind","bl","borrow","","","","","","","","","","","","","","","borrow_mut","","","","","","","","","","","","","","","bp","bpl","bx","call","ch","cl","clone","","","","clone_into","","","","clone_to_uninit","","","","cmovnz","cmovz","cmp","","","cx","dec","","","","","","dh","di","dil","dl","drop","","dump","dx","eax","ebp","ebx","ecx","edi","edx","esi","esp","from","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","","inc","","","","","","indirect","","","","indirect_base_index","","","","indirect_disp","","","","insn","into","","","","","","","","","","","","","","","into_code","jmp","jnz","jz","mov","","","","","","","","","","","","","","","","","new","","","nop","pop","","push","","r10","r10d","r10l","r10w","r11","r11d","r11l","r11w","r12","r12d","r12l","r12w","r13","r13d","r13l","r13w","r14","r14d","r14l","r14w","r15","r15d","r15l","r15w","r8","r8d","r8l","r8w","r9","r9d","r9l","r9w","rax","rbp","rbx","rcx","rdi","rdx","ret","rsi","rsp","si","sil","sp","spl","sub","","test","","","to_owned","","","","try_from","","","","","","","","","","","","","","","try_into","","","","","","","","","","","","","","","type_id","","","","","","","","","","","","","","","with_profile","xor","Add","Call","Cmovnz","Cmovz","Cmp","Dec","Inc","Jmp","Jnz","Jz","Mov","Pop","Push","Sub","Test","Xor","add","call","cmovnz","cmovz","cmp","dec","inc","jmp","jnz","jz","mov","pop","push","sub","test","xor"],"q":[[0,"juicebox_asm"],[309,"juicebox_asm::insn"],[341,"juicebox_asm::asm"],[342,"juicebox_asm::reg"],[343,"juicebox_asm::mem"],[344,"juicebox_asm::imm"],[345,"juicebox_asm::rt"],[346,"core::convert"],[347,"juicebox_asm::label"],[348,"alloc::vec"],[349,"core::result"],[350,"core::any"]],"i":"```````````````d000000000AlBf0Aj1313Bd3A`AhBnCfnAbAdjhAf;<>:=9876543210;<;<;><<10;<10;<10;<>>>>>;>>>>>><;<<:==;00000000>:=99988888777777766666666666543210;<>>>>>>543254325432`>:=9876543210;<>>>>>>>>>>>>>>>>>>>>>>:=>>>>>10<;10<;10<;10<;10<;10<;10<;10<;111111>11;<;<>>>>>10;<>:=9876543210;<>:=9876543210;<>:=9876543210;<=>````````````````DdDfDhDjDlDnE`EbEdEfEhEjElEnF`Fb","f":"```````````````{{{f{bd}}hj}l}{{{f{bd}}hh}l}{{{f{bd}}nA`}l}{{{f{bd}}AbA`}l}{{{f{bd}}AdA`}l}{{{f{bd}}jA`}l}{{{f{bd}}jh}l}{{{f{bd}}AfAf}l}{{{f{bd}}AbAh}l}{{{f{bd}}AbAj}l}{{{f{bAl}}c}e{{Bb{{B`{An}}}}}{}}````{{{f{bd}}{f{bBd}}}l}`{f{{f{c}}}{}}00000000000000{{{f{b}}}{{f{bc}}}{}}00000000000000```{{{f{bd}}h}l}``{{{f{h}}}h}{{{f{Af}}}Af}{{{f{Aj}}}Aj}{{{f{Bf}}}Bf}{{f{f{bc}}}l{}}000{fl}000{{{f{bd}}hh}l}00={{{f{bd}}nA`}l}`{{{f{bd}}Af}l}{{{f{bd}}j}l}:{{{f{bd}}Ad}l}{{{f{bd}}n}l}{{{f{bd}}Ab}l}````{{{f{bBd}}}l}{{{f{bAl}}}l}{{{f{Al}}}l}`````````{cc{}}000{AnA`}{BhA`}{BjAh}3{AnAh}{BlAh}{BhAh}{AnBn}{BjBn}8{C`Bn}{CbBn}{BlBn}{BhBn}<{CdCf}{ChCf}{C`Cf}{CbCf}{BlCf}{BjCf}{AnCf}{BhCf}{CjCf}{ClCf}{cc{}}0000000{{{f{bd}}Af}l}{{{f{bd}}n}l}{{{f{bd}}Ab}l}{{{f{bd}}Ad}l}{{{f{bd}}j}l}{{{f{bd}}h}l}{hn}{hAb}{hAd}{hj}{{hh}n}{{hh}Ab}{{hh}Ad}{{hh}j}{{hCb}n}{{hCb}Ab}{{hCb}Ad}{{hCb}j}`{{}c{}}00000000000000{d{{Cn{An}}}}{{{f{bd}}{f{bBd}}}l}00{{{f{bd}}nBf}l}{{{f{bd}}AjAh}l}{{{f{bd}}AbAh}l}{{{f{bd}}AbAj}l}{{{f{bd}}AdAf}l}{{{f{bd}}jh}l}{{{f{bd}}BfBf}l}{{{f{bd}}AjAj}l}{{{f{bd}}AfAf}l}{{{f{bd}}BfA`}l}{{{f{bd}}hj}l}{{{f{bd}}AfAd}l}{{{f{bd}}AjAb}l}{{{f{bd}}Bfn}l}{{{f{bd}}hCf}l}{{{f{bd}}AfBn}l}{{{f{bd}}hh}l}{{}d}{{}Bd}{{}Al}{{{f{bd}}}l}{{{f{bd}}h}l}{{{f{bd}}Aj}l}10``````````````````````````````````````2``````6{{{f{bd}}nA`}l}?7{{{f{bd}}AbAh}l}{fc{}}000{c{{D`{e}}}{}{}}00000000000000{{}{{D`{c}}}{}}00000000000000{fDb}000000000000009<````````````````{{{f{bDd}}ce}l{}{}}{{{f{bDf}}c}l{}}{{{f{bDh}}ce}l{}{}}{{{f{bDj}}ce}l{}{}}{{{f{bDl}}ce}l{}{}}{{{f{bDn}}c}l{}}{{{f{bE`}}c}l{}}{{{f{bEb}}c}l{}}{{{f{bEd}}c}l{}}{{{f{bEf}}c}l{}}{{{f{bEh}}ce}l{}{}}{{{f{bEj}}c}l{}}{{{f{bEl}}c}l{}}{{{f{bEn}}ce}l{}{}}{{{f{bF`}}ce}l{}{}}{{{f{bFb}}ce}l{}{}}","D":"Ll","p":[[0,"mut"],[5,"Asm",0,341],[1,"reference"],[6,"Reg64",0,342],[5,"Mem64",0,343],[1,"unit"],[5,"Mem8",0,343],[5,"Imm8",0,344],[5,"Mem16",0,343],[5,"Mem32",0,343],[6,"Reg32",0,342],[5,"Imm16",0,344],[6,"Reg16",0,342],[5,"Runtime",0,345],[1,"u8"],[1,"slice"],[10,"AsRef",346],[5,"Label",0,347],[6,"Reg8",0,342],[1,"i8"],[1,"i16"],[1,"u16"],[5,"Imm32",0,344],[1,"u32"],[1,"i32"],[1,"u64"],[5,"Imm64",0,344],[1,"i64"],[1,"usize"],[1,"isize"],[5,"Vec",348],[6,"Result",349],[5,"TypeId",350],[10,"Add",309],[10,"Call",309],[10,"Cmovnz",309],[10,"Cmovz",309],[10,"Cmp",309],[10,"Dec",309],[10,"Inc",309],[10,"Jmp",309],[10,"Jnz",309],[10,"Jz",309],[10,"Mov",309],[10,"Pop",309],[10,"Push",309],[10,"Sub",309],[10,"Test",309],[10,"Xor",309]],"r":[[0,341],[1,344],[2,344],[3,344],[4,344],[5,347],[6,343],[7,343],[8,343],[9,343],[10,342],[11,342],[12,342],[13,342],[14,345]],"b":[[15,"impl-Add%3CReg64,+Mem64%3E-for-Asm"],[16,"impl-Add%3CReg64,+Reg64%3E-for-Asm"],[17,"impl-Add%3CMem8,+Imm8%3E-for-Asm"],[18,"impl-Add%3CMem16,+Imm8%3E-for-Asm"],[19,"impl-Add%3CMem32,+Imm8%3E-for-Asm"],[20,"impl-Add%3CMem64,+Imm8%3E-for-Asm"],[21,"impl-Add%3CMem64,+Reg64%3E-for-Asm"],[22,"impl-Add%3CReg32,+Reg32%3E-for-Asm"],[23,"impl-Add%3CMem16,+Imm16%3E-for-Asm"],[24,"impl-Add%3CMem16,+Reg16%3E-for-Asm"],[82,"impl-Cmp%3CReg64,+Reg64%3E-for-Asm"],[83,"impl-Cmp%3CMem16,+Imm16%3E-for-Asm"],[84,"impl-Cmp%3CMem8,+Imm8%3E-for-Asm"],[86,"impl-Dec%3CReg32%3E-for-Asm"],[87,"impl-Dec%3CMem64%3E-for-Asm"],[88,"impl-Dec%3CReg64%3E-for-Asm"],[89,"impl-Dec%3CMem32%3E-for-Asm"],[90,"impl-Dec%3CMem8%3E-for-Asm"],[91,"impl-Dec%3CMem16%3E-for-Asm"],[112,"impl-From%3Cu8%3E-for-Imm8"],[113,"impl-From%3Ci8%3E-for-Imm8"],[114,"impl-From%3Ci16%3E-for-Imm16"],[116,"impl-From%3Cu8%3E-for-Imm16"],[117,"impl-From%3Cu16%3E-for-Imm16"],[118,"impl-From%3Ci8%3E-for-Imm16"],[119,"impl-From%3Cu8%3E-for-Imm32"],[120,"impl-From%3Ci16%3E-for-Imm32"],[122,"impl-From%3Cu32%3E-for-Imm32"],[123,"impl-From%3Ci32%3E-for-Imm32"],[124,"impl-From%3Cu16%3E-for-Imm32"],[125,"impl-From%3Ci8%3E-for-Imm32"],[127,"impl-From%3Cu64%3E-for-Imm64"],[128,"impl-From%3Ci64%3E-for-Imm64"],[129,"impl-From%3Cu32%3E-for-Imm64"],[130,"impl-From%3Ci32%3E-for-Imm64"],[131,"impl-From%3Cu16%3E-for-Imm64"],[132,"impl-From%3Ci16%3E-for-Imm64"],[133,"impl-From%3Cu8%3E-for-Imm64"],[134,"impl-From%3Ci8%3E-for-Imm64"],[135,"impl-From%3Cusize%3E-for-Imm64"],[136,"impl-From%3Cisize%3E-for-Imm64"],[145,"impl-Inc%3CReg32%3E-for-Asm"],[146,"impl-Inc%3CMem8%3E-for-Asm"],[147,"impl-Inc%3CMem16%3E-for-Asm"],[148,"impl-Inc%3CMem32%3E-for-Asm"],[149,"impl-Inc%3CMem64%3E-for-Asm"],[150,"impl-Inc%3CReg64%3E-for-Asm"],[183,"impl-Mov%3CMem8,+Reg8%3E-for-Asm"],[184,"impl-Mov%3CReg16,+Imm16%3E-for-Asm"],[185,"impl-Mov%3CMem16,+Imm16%3E-for-Asm"],[186,"impl-Mov%3CMem16,+Reg16%3E-for-Asm"],[187,"impl-Mov%3CMem32,+Reg32%3E-for-Asm"],[188,"impl-Mov%3CMem64,+Reg64%3E-for-Asm"],[189,"impl-Mov%3CReg8,+Reg8%3E-for-Asm"],[190,"impl-Mov%3CReg16,+Reg16%3E-for-Asm"],[191,"impl-Mov%3CReg32,+Reg32%3E-for-Asm"],[192,"impl-Mov%3CReg8,+Imm8%3E-for-Asm"],[193,"impl-Mov%3CReg64,+Mem64%3E-for-Asm"],[194,"impl-Mov%3CReg32,+Mem32%3E-for-Asm"],[195,"impl-Mov%3CReg16,+Mem16%3E-for-Asm"],[196,"impl-Mov%3CReg8,+Mem8%3E-for-Asm"],[197,"impl-Mov%3CReg64,+Imm64%3E-for-Asm"],[198,"impl-Mov%3CReg32,+Imm32%3E-for-Asm"],[199,"impl-Mov%3CReg64,+Reg64%3E-for-Asm"],[204,"impl-Pop%3CReg64%3E-for-Asm"],[205,"impl-Pop%3CReg16%3E-for-Asm"],[206,"impl-Push%3CReg64%3E-for-Asm"],[207,"impl-Push%3CReg16%3E-for-Asm"],[253,"impl-Sub%3CReg64,+Reg64%3E-for-Asm"],[254,"impl-Sub%3CMem8,+Imm8%3E-for-Asm"],[255,"impl-Test%3CReg32,+Reg32%3E-for-Asm"],[256,"impl-Test%3CReg64,+Reg64%3E-for-Asm"],[257,"impl-Test%3CMem16,+Imm16%3E-for-Asm"]],"c":"OjAAAAAAAAA=","e":"OzAAAAEAAO8ADQAQAAkAGwADACAAQQBkAAgAcQACAHUABAB7AAMAgAAJAJIABQC1ABMAzQApAPgAOwA1AQAA"}],["tiny_vm",{"t":"PPPPPPPFPPPFPGGFNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNNHHHNNNNNNNNNNNNNNNNNNNNNNN","n":["A","Add","Addi","B","Branch","BranchZero","C","Fixup","Halt","Load","LoadImm","PhysAddr","Store","TinyInsn","TinyReg","TinyVm","bind","borrow","","","","","borrow_mut","","","","","clone","","clone_into","","clone_to_uninit","","dump","eq","","fmt","","from","","","","","interp","into","","","","","","jit","make_tinyvm_fib","make_tinyvm_jit_perf","make_tinyvm_jit_test","new","","read_mem","read_reg","to_owned","","try_from","","","","","try_into","","","","","type_id","","","","","write_mem","write_reg"],"q":[[0,"tiny_vm"],[77,"alloc::vec"],[78,"core::fmt"],[79,"core::result"],[80,"core::any"]],"i":"nf01001`000`0```bAhA`24310243434343043431024301102430```02004310243102431024300","f":"````````````````{{b{j{d{h{f}}}}}l}{j{{j{c}}}{}}0000{{{j{d}}}{{j{dc}}}{}}0000{{{j{n}}}n}{{{j{f}}}f}{{j{j{dc}}}l{}}0{jl}0{{{j{A`}}}l}{{{j{n}}{j{n}}}Ab}{{{j{f}}{j{f}}}Ab}{{{j{n}}{j{dAd}}}Af}{{{j{f}}{j{dAd}}}Af}{cc{}}0000{{{j{dA`}}}l}{AhAj}{{}c{}}00002{Al{{h{f}}}}{{}{{h{f}}}}0{{{h{f}}}A`}{Ajb}{{{j{A`}}Ah}Al}{{{j{A`}}n}Al}{jc{}}0{c{{An{e}}}{}{}}0000{{}{{An{c}}}{}}0000{jB`}0000{{{j{dA`}}AhAl}l}{{{j{dA`}}nAl}l}","D":"Dj","p":[[5,"Fixup",0],[0,"mut"],[6,"TinyInsn",0],[5,"Vec",77],[1,"reference"],[1,"unit"],[6,"TinyReg",0],[5,"TinyVm",0],[1,"bool"],[5,"Formatter",78],[8,"Result",78],[5,"PhysAddr",0],[1,"usize"],[1,"u16"],[6,"Result",79],[5,"TypeId",80]],"r":[],"b":[],"c":"OjAAAAAAAAA=","e":"OzAAAAEAACgABwABAAAABAAAAAcAAAASAA8AIwADAC0AAAA7ABAA"}]]')); if (typeof exports !== 'undefined') exports.searchIndex = searchIndex; else if (window.initSearch) window.initSearch(searchIndex); -//{"start":39,"fragment_lengths":[111,111,112,8192,1542]} \ No newline at end of file +//{"start":39,"fragment_lengths":[111,111,112,8229,1542]} \ No newline at end of file diff --git a/src/bf/bf.rs.html b/src/bf/bf.rs.html index b29403b..556b131 100644 --- a/src/bf/bf.rs.html +++ b/src/bf/bf.rs.html @@ -337,7 +337,72 @@ 336 337 338 -339
//! Brainfuck VM.
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//! Brainfuck VM.
 //!
 //! This example implements a simple
 //! [brainfuck](https://en.wikipedia.org/wiki/Brainfuck) interpreter
@@ -514,11 +579,20 @@
     // Use callee saved registers to hold vm state, such that we don't need to
     // save any state before calling out to putchar.
     let dmem_base = Reg64::rbx;
-    let dmem_idx = Reg64::r12;
+    let dmem_size = Reg64::r12;
+    let dmem_idx = Reg64::r13;
 
     let mut asm = Asm::new();
+
+    // Save callee saved registers before we tamper them.
+    asm.push(dmem_base);
+    asm.push(dmem_size);
+    asm.push(dmem_idx);
+
     // Move data memory pointer (argument on jit entry) into correct register.
     asm.mov(dmem_base, Reg64::rdi);
+    // Move data memory size into correct register.
+    asm.mov(dmem_size, Reg64::rsi);
     // Clear data memory index.
     asm.xor(dmem_idx, dmem_idx);
 
@@ -526,17 +600,28 @@
     // given '[]' pair.
     let mut label_stack = Vec::new();
 
+    // Label to jump to when a data pointer overflow is detected.
+    let mut oob_ov = Label::new();
+    // Label to jump to when a data pointer underflow is detected.
+    let mut oob_uv = Label::new();
+
     // Generate code for each instruction in the bf program.
     let mut pc = 0;
     while pc < vm.imem.len() {
         match vm.imem[pc] {
             '>' => {
-                // TODO: generate runtime bounds check.
-                asm.inc(dmem_idx);
+                asm.inc(dmem_idx);
+
+                // Check for data pointer overflow and jump to error handler if needed.
+                asm.cmp(dmem_idx, dmem_size);
+                asm.jz(&mut oob_ov);
             }
             '<' => {
-                // TODO: generate runtime bounds check.
-                asm.dec(dmem_idx);
+                // Check for data pointer underflow and jump to error handler if needed.
+                asm.test(dmem_idx, dmem_idx);
+                asm.jz(&mut oob_uv);
+
+                asm.dec(dmem_idx);
             }
             '+' => {
                 // Apply optimization to fold consecutive '+' instructions to a
@@ -546,10 +631,8 @@
                     1 => {
                         asm.inc(Mem8::indirect_base_index(dmem_base, dmem_idx));
                     }
-                    cnt if cnt <= i8::MAX as usize => {
-                        // For add m64, imm8, the immediate is sign-extend and
-                        // hence treated as signed.
-                        asm.add(
+                    cnt if cnt <= u8::MAX as usize => {
+                        asm.add(
                             Mem8::indirect_base_index(dmem_base, dmem_idx),
                             Imm8::from(cnt as u8),
                         );
@@ -569,10 +652,8 @@
                     1 => {
                         asm.dec(Mem8::indirect_base_index(dmem_base, dmem_idx));
                     }
-                    cnt if cnt <= i8::MAX as usize => {
-                        // For sub m64, imm8, the immediate is sign-extend and
-                        // hence treated as signed.
-                        asm.sub(
+                    cnt if cnt <= u8::MAX as usize => {
+                        asm.sub(
                             Mem8::indirect_base_index(dmem_base, dmem_idx),
                             Imm8::from(cnt as u8),
                         );
@@ -639,30 +720,48 @@
         pc += 1;
     }
 
-    // Return from bf program.
-    asm.ret();
+    let mut ret_epilogue = Label::new();
+
+    // Successful return from bf program.
+    asm.xor(Reg64::rax, Reg64::rax);
+    asm.bind(&mut ret_epilogue);
+    // Restore callee saved registers before returning from jit.
+    asm.pop(dmem_idx);
+    asm.pop(dmem_size);
+    asm.pop(dmem_base);
+    asm.ret();
+
+    // Return because of data pointer overflow.
+    asm.bind(&mut oob_ov);
+    asm.mov(Reg64::rax, Imm64::from(1));
+    asm.jmp(&mut ret_epilogue);
+
+    // Return because of data pointer underflow.
+    asm.bind(&mut oob_uv);
+    asm.mov(Reg64::rax, Imm64::from(2));
+    asm.jmp(&mut ret_epilogue);
 
     if !label_stack.is_empty() {
         panic!("encountered un-balanced brackets, left-over '[' after jitting bf program")
     }
 
-    // Execute jitted bf program.
+    // Get function pointer to jitted bf program.
     let mut rt = Runtime::new();
-    let bf_entry = unsafe { rt.add_code::<extern "C" fn(*mut u8)>(asm.into_code()) };
-    bf_entry(&mut vm.dmem as *mut u8);
+    let bf_entry = unsafe { rt.add_code::<extern "C" fn(*mut u8, usize) -> u64>(asm.into_code()) };
+
+    // Execute jitted bf program.
+    match bf_entry(&mut vm.dmem as *mut u8, vm.dmem.len()) {
+        0 => {}
+        1 => panic!("oob: data pointer overflow"),
+        2 => panic!("oob: data pointer underflow"),
+        _ => unreachable!(),
+    }
 }
 
 // -- MAIN ---------------------------------------------------------------------
 
 fn main() {
-    // https://en.wikipedia.org/wiki/Brainfuck#Adding_two_values
-    //let inp = "++>+++++ [<+>-] ++++++++[<++++++>-]<.";
-    //println!("add-print-7 (wikipedia.org) - interp");
-    //run_interp(inp);
-    //println!("add-print-7 (wikipedia.org) - jit");
-    //run_jit(inp);
-
-    // https://en.wikipedia.org/wiki/Brainfuck#Hello_World!
+    // https://en.wikipedia.org/wiki/Brainfuck#Hello_World!
     let inp = "++++++++[>++++[>++>+++>+++>+<<<<-]>+>+>->>+[<]<-]>>.>---.+++++++..+++.>>.<-.<.+++.------.--------.>>+.>++.";
     println!("hello-world (wikipedia.org) - interp");
     run_interp(inp);
@@ -676,4 +775,35 @@
     println!("hello-world (programmingwiki.de) - jit");
     run_jit(inp);
 }
+
+#[cfg(test)]
+mod test {
+    use super::*;
+
+    #[test]
+    fn data_ptr_no_overflow() {
+        let inp = std::iter::repeat('>').take(255).collect::<String>();
+        run_jit(&inp);
+    }
+
+    #[test]
+    #[should_panic]
+    fn data_ptr_overflow() {
+        let inp = std::iter::repeat('>').take(255 + 1).collect::<String>();
+        run_jit(&inp);
+    }
+
+    #[test]
+    fn data_ptr_no_underflow() {
+        let inp = ">><< ><";
+        run_jit(inp);
+    }
+
+    #[test]
+    #[should_panic]
+    fn data_ptr_underflow() {
+        let inp = ">><< >< <";
+        run_jit(&inp);
+    }
+}
 
\ No newline at end of file diff --git a/src/fib/fib.rs.html b/src/fib/fib.rs.html index 0b7a4bf..32ebea0 100644 --- a/src/fib/fib.rs.html +++ b/src/fib/fib.rs.html @@ -124,7 +124,7 @@ let sum = Reg64::rax; let tmp = Reg64::rcx; - let prv = Reg64::rbx; + let prv = Reg64::rdx; asm.mov(tmp, Imm64::from(0)); asm.mov(prv, Imm64::from(1)); diff --git a/src/juicebox_asm/insn/cmp.rs.html b/src/juicebox_asm/insn/cmp.rs.html index 35bb5b7..166f22f 100644 --- a/src/juicebox_asm/insn/cmp.rs.html +++ b/src/juicebox_asm/insn/cmp.rs.html @@ -12,8 +12,14 @@ 11 12 13 -14
use super::Cmp;
-use crate::{Asm, Imm16, Imm8, Mem16, Mem8};
+14
+15
+16
+17
+18
+19
+20
use super::Cmp;
+use crate::{Asm, Imm16, Imm8, Mem16, Mem8, Reg64};
 
 impl Cmp<Mem8, Imm8> for Asm {
     fn cmp(&mut self, op1: Mem8, op2: Imm8) {
@@ -26,4 +32,10 @@
         self.encode_mi(0x81, 0x7, op1, op2);
     }
 }
+
+impl Cmp<Reg64, Reg64> for Asm {
+    fn cmp(&mut self, op1: Reg64, op2: Reg64) {
+        self.encode_rr(&[0x3b], op1, op2);
+    }
+}
 
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