From 3e184b0b47d203cd37089296e0c49c9219c83b26 Mon Sep 17 00:00:00 2001
From: Johannes Stoelp <johannes.stoelp@gmail.com>
Date: Mon, 27 Feb 2023 20:40:26 +0100
Subject: Move instruction implementation in sub module and introduce insn
 prelude

---
 src/insn/mov.rs     | 105 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 src/insn/prelude.rs |   6 +++
 2 files changed, 111 insertions(+)
 create mode 100644 src/insn/mov.rs
 create mode 100644 src/insn/prelude.rs

(limited to 'src/insn')

diff --git a/src/insn/mov.rs b/src/insn/mov.rs
new file mode 100644
index 0000000..d930ade
--- /dev/null
+++ b/src/insn/mov.rs
@@ -0,0 +1,105 @@
+use super::prelude::*;
+
+// -- MOV : reg reg
+
+impl Mov<Reg64, Reg64> for Asm {
+    fn mov(&mut self, op1: Reg64, op2: Reg64) {
+        self.encode_rr(0x89, op1, op2);
+    }
+}
+
+impl Mov<Reg32, Reg32> for Asm {
+    fn mov(&mut self, op1: Reg32, op2: Reg32) {
+        self.encode_rr(0x89, op1, op2);
+    }
+}
+
+impl Mov<Reg16, Reg16> for Asm {
+    fn mov(&mut self, op1: Reg16, op2: Reg16) {
+        self.encode_rr(0x89, op1, op2);
+    }
+}
+
+impl Mov<Reg8, Reg8> for Asm {
+    fn mov(&mut self, op1: Reg8, op2: Reg8) {
+        self.encode_rr(0x88, op1, op2);
+    }
+}
+
+// -- MOV : mem reg
+
+impl Mov<MemOp, Reg64> for Asm {
+    fn mov(&mut self, op1: MemOp, op2: Reg64) {
+        self.encode_mr(0x89, op1, op2);
+    }
+}
+
+impl Mov<MemOp, Reg32> for Asm {
+    fn mov(&mut self, op1: MemOp, op2: Reg32) {
+        self.encode_mr(0x89, op1, op2);
+    }
+}
+
+impl Mov<MemOp, Reg16> for Asm {
+    fn mov(&mut self, op1: MemOp, op2: Reg16) {
+        self.encode_mr(0x89, op1, op2);
+    }
+}
+
+impl Mov<MemOp, Reg8> for Asm {
+    fn mov(&mut self, op1: MemOp, op2: Reg8) {
+        self.encode_mr(0x88, op1, op2);
+    }
+}
+
+// -- MOV : reg mem
+
+impl Mov<Reg64, MemOp> for Asm {
+    fn mov(&mut self, op1: Reg64, op2: MemOp) {
+        self.encode_rm(0x8b, op1, op2);
+    }
+}
+
+impl Mov<Reg32, MemOp> for Asm {
+    fn mov(&mut self, op1: Reg32, op2: MemOp) {
+        self.encode_rm(0x8b, op1, op2);
+    }
+}
+
+impl Mov<Reg16, MemOp> for Asm {
+    fn mov(&mut self, op1: Reg16, op2: MemOp) {
+        self.encode_rm(0x8b, op1, op2);
+    }
+}
+
+impl Mov<Reg8, MemOp> for Asm {
+    fn mov(&mut self, op1: Reg8, op2: MemOp) {
+        self.encode_rm(0x8a, op1, op2);
+    }
+}
+
+// -- MOV : reg imm
+
+impl Mov<Reg64, Imm64> for Asm {
+    fn mov(&mut self, op1: Reg64, op2: Imm64) {
+        self.encode_oi(0xb8, op1, op2);
+    }
+}
+
+impl Mov<Reg32, Imm32> for Asm {
+    fn mov(&mut self, op1: Reg32, op2: Imm32) {
+        self.encode_oi(0xb8, op1, op2);
+    }
+}
+
+impl Mov<Reg16, Imm16> for Asm {
+    fn mov(&mut self, op1: Reg16, op2: Imm16) {
+        self.encode_oi(0xb8, op1, op2);
+    }
+}
+
+impl Mov<Reg8, Imm8> for Asm {
+    fn mov(&mut self, op1: Reg8, op2: Imm8) {
+        self.encode_oi(0xb0, op1, op2);
+    }
+}
diff --git a/src/insn/prelude.rs b/src/insn/prelude.rs
new file mode 100644
index 0000000..703417a
--- /dev/null
+++ b/src/insn/prelude.rs
@@ -0,0 +1,6 @@
+pub use crate::Asm;
+pub use crate::MemOp;
+pub use crate::{Imm16, Imm32, Imm64, Imm8};
+pub use crate::{Reg16, Reg32, Reg64, Reg8};
+
+pub use crate::insn::Mov;
-- 
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