From 5289cbf5331dfd0d0c2242a7e7c8030aa4032c7e Mon Sep 17 00:00:00 2001 From: johannst Date: Sat, 7 Dec 2024 01:01:45 +0000 Subject: deploy: 9c3c3fd923d894d2351eb22129ea693eb98fa8ff --- src/juicebox_asm/insn/add.rs.html | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) (limited to 'src/juicebox_asm/insn/add.rs.html') diff --git a/src/juicebox_asm/insn/add.rs.html b/src/juicebox_asm/insn/add.rs.html index 6146498..e62bc4a 100644 --- a/src/juicebox_asm/insn/add.rs.html +++ b/src/juicebox_asm/insn/add.rs.html @@ -1,5 +1,5 @@ -add.rs - source
- 
1
+add.rs - source
juicebox_asm/insn/
add.rs
+1
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@@ -25,7 +25,18 @@
 24
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-
use super::Add;
+27
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use super::Add;
 use crate::{Asm, Imm16, MemOp, Reg16, Reg32, Reg64};
 
 impl Add<Reg64, Reg64> for Asm {
@@ -40,6 +51,12 @@
     }
 }
 
+impl Add<MemOp, Reg64> for Asm {
+    fn add(&mut self, op1: MemOp, op2: Reg64) {
+        self.encode_mr(0x01, op1, op2);
+    }
+}
+
 impl Add<MemOp, Reg16> for Asm {
     fn add(&mut self, op1: MemOp, op2: Reg16) {
         self.encode_mr(0x01, op1, op2);
@@ -51,4 +68,10 @@
         self.encode_mi(0x81, 0, op1, op2);
     }
 }
+
+impl Add<Reg64, MemOp> for Asm {
+    fn add(&mut self, op1: Reg64, op2: MemOp) {
+        self.encode_rm(0x03, op1, op2);
+    }
+}
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