From 52a0308e18fbbec25f0e9f31ec8f11589a35f351 Mon Sep 17 00:00:00 2001 From: johannst Date: Mon, 18 Mar 2024 22:02:54 +0000 Subject: deploy: 7653ced7e8ce18b9ada2b666c63832007f8becf2 --- src/juicebox_asm/asm.rs.html | 6 ++++-- src/juicebox_asm/insn.rs.html | 32 ++++++++++++++++++++++++++++++++ src/juicebox_asm/insn/add.rs.html | 4 ++-- src/juicebox_asm/insn/cmovnz.rs.html | 18 ++++++++++++++++++ src/juicebox_asm/insn/cmovz.rs.html | 18 ++++++++++++++++++ src/juicebox_asm/insn/mov.rs.html | 8 ++++---- src/juicebox_asm/insn/test.rs.html | 4 ++-- 7 files changed, 80 insertions(+), 10 deletions(-) create mode 100644 src/juicebox_asm/insn/cmovnz.rs.html create mode 100644 src/juicebox_asm/insn/cmovz.rs.html (limited to 'src/juicebox_asm') diff --git a/src/juicebox_asm/asm.rs.html b/src/juicebox_asm/asm.rs.html index e58260d..4418397 100644 --- a/src/juicebox_asm/asm.rs.html +++ b/src/juicebox_asm/asm.rs.html @@ -343,6 +343,7 @@ 342 343 344 +345 
//! The `x64` jit assembler.
 
 use crate::*;
@@ -437,7 +438,7 @@
     // -- Encode utilities.
 
     /// Encode an register-register instruction.
-    pub(crate) fn encode_rr<T: Reg>(&mut self, opc: u8, op1: T, op2: T)
+    pub(crate) fn encode_rr<T: Reg>(&mut self, opc: &[u8], op1: T, op2: T)
     where
         Self: EncodeRR<T>,
     {
@@ -454,7 +455,8 @@
         let rex = <Self as EncodeRR<T>>::rex(op1, op2);
 
         self.emit_optional(&[prefix, rex]);
-        self.emit(&[opc, modrm]);
+        self.emit(opc);
+        self.emit(&[modrm]);
     }
 
     /// Encode an offset-immediate instruction.
diff --git a/src/juicebox_asm/insn.rs.html b/src/juicebox_asm/insn.rs.html
index 7198773..029258c 100644
--- a/src/juicebox_asm/insn.rs.html
+++ b/src/juicebox_asm/insn.rs.html
@@ -86,10 +86,28 @@
 85
 86
 87
+88
+89
+90
+91
+92
+93
+94
+95
+96
+97
+98
+99
+100
+101
+102
+103
 
//! Trait definitions of various instructions.
 
 mod add;
 mod call;
+mod cmovnz;
+mod cmovz;
 mod cmp;
 mod dec;
 mod jmp;
@@ -114,6 +132,20 @@
     fn call(&mut self, op1: T);
 }
 
+pub trait Cmovnz<T, U> {
+    /// Emit a (conditional) move if not zero instruction.
+    ///
+    /// Move is only commited if (ZF=0).
+    fn cmovnz(&mut self, op1: T, op2: U);
+}
+
+pub trait Cmovz<T, U> {
+    /// Emit a (conditional) move if zero instruction.
+    ///
+    /// Move is only commited if (ZF=1).
+    fn cmovz(&mut self, op1: T, op2: U);
+}
+
 /// Trait for [`cmp`](https://www.felixcloutier.com/x86/cmp) instruction kinds.
 pub trait Cmp<T, U> {
     /// Emit a compare instruction.
diff --git a/src/juicebox_asm/insn/add.rs.html b/src/juicebox_asm/insn/add.rs.html
index a6ac132..6146498 100644
--- a/src/juicebox_asm/insn/add.rs.html
+++ b/src/juicebox_asm/insn/add.rs.html
@@ -30,13 +30,13 @@
 
 impl Add<Reg64, Reg64> for Asm {
     fn add(&mut self, op1: Reg64, op2: Reg64) {
-        self.encode_rr(0x01, op1, op2);
+        self.encode_rr(&[0x01], op1, op2);
     }
 }
 
 impl Add<Reg32, Reg32> for Asm {
     fn add(&mut self, op1: Reg32, op2: Reg32) {
-        self.encode_rr(0x01, op1, op2);
+        self.encode_rr(&[0x01], op1, op2);
     }
 }
 
diff --git a/src/juicebox_asm/insn/cmovnz.rs.html b/src/juicebox_asm/insn/cmovnz.rs.html
new file mode 100644
index 0000000..29bfb58
--- /dev/null
+++ b/src/juicebox_asm/insn/cmovnz.rs.html
@@ -0,0 +1,18 @@
+cmovnz.rs - source

+    
1
+2
+3
+4
+5
+6
+7
+8
+
use super::Cmovnz;
+use crate::{Asm, Reg64};
+
+impl Cmovnz<Reg64, Reg64> for Asm {
+    fn cmovnz(&mut self, op1: Reg64, op2: Reg64) {
+        self.encode_rr(&[0x0f, 0x45], op2, op1);
+    }
+}
+

\ No newline at end of file
diff --git a/src/juicebox_asm/insn/cmovz.rs.html b/src/juicebox_asm/insn/cmovz.rs.html
new file mode 100644
index 0000000..ecb62f1
--- /dev/null
+++ b/src/juicebox_asm/insn/cmovz.rs.html
@@ -0,0 +1,18 @@
+cmovz.rs - source

+    
1
+2
+3
+4
+5
+6
+7
+8
+
use super::Cmovz;
+use crate::{Asm, Reg64};
+
+impl Cmovz<Reg64, Reg64> for Asm {
+    fn cmovz(&mut self, op1: Reg64, op2: Reg64) {
+        self.encode_rr(&[0x0f, 0x44], op2, op1);
+    }
+}
+

\ No newline at end of file
diff --git a/src/juicebox_asm/insn/mov.rs.html b/src/juicebox_asm/insn/mov.rs.html
index 6d6e6e7..8f10e31 100644
--- a/src/juicebox_asm/insn/mov.rs.html
+++ b/src/juicebox_asm/insn/mov.rs.html
@@ -120,25 +120,25 @@
 
 impl Mov<Reg64, Reg64> for Asm {
     fn mov(&mut self, op1: Reg64, op2: Reg64) {
-        self.encode_rr(0x89, op1, op2);
+        self.encode_rr(&[0x89], op1, op2);
     }
 }
 
 impl Mov<Reg32, Reg32> for Asm {
     fn mov(&mut self, op1: Reg32, op2: Reg32) {
-        self.encode_rr(0x89, op1, op2);
+        self.encode_rr(&[0x89], op1, op2);
     }
 }
 
 impl Mov<Reg16, Reg16> for Asm {
     fn mov(&mut self, op1: Reg16, op2: Reg16) {
-        self.encode_rr(0x89, op1, op2);
+        self.encode_rr(&[0x89], op1, op2);
     }
 }
 
 impl Mov<Reg8, Reg8> for Asm {
     fn mov(&mut self, op1: Reg8, op2: Reg8) {
-        self.encode_rr(0x88, op1, op2);
+        self.encode_rr(&[0x88], op1, op2);
     }
 }
 
diff --git a/src/juicebox_asm/insn/test.rs.html b/src/juicebox_asm/insn/test.rs.html
index 6a0372d..53a4e39 100644
--- a/src/juicebox_asm/insn/test.rs.html
+++ b/src/juicebox_asm/insn/test.rs.html
@@ -24,13 +24,13 @@
 
 impl Test<Reg64, Reg64> for Asm {
     fn test(&mut self, op1: Reg64, op2: Reg64) {
-        self.encode_rr(0x85, op1, op2);
+        self.encode_rr(&[0x85], op1, op2);
     }
 }
 
 impl Test<Reg32, Reg32> for Asm {
     fn test(&mut self, op1: Reg32, op2: Reg32) {
-        self.encode_rr(0x85, op1, op2);
+        self.encode_rr(&[0x85], op1, op2);
     }
 }
 
-- 
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