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authorjohannst <johannst@users.noreply.github.com>2021-02-28 20:37:15 +0000
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+ <h1><a class="header" href="#armv7a" id="armv7a">armv7a</a></h1>
+<p>keywords: arm, armv7, abi</p>
+<ul>
+<li>ISA type: <code>RISC</code></li>
+<li>Endianness: <code>little</code>, <code>big</code></li>
+</ul>
+<h2><a class="header" href="#registers" id="registers">Registers</a></h2>
+<h3><a class="header" href="#general-purpose-registers" id="general-purpose-registers">General purpose registers</a></h3>
+<pre><code class="language-markdown">bytes
+[3:0] alt desc
+---------------------------------------------
+r0-r12 general purpose registers
+r11 fp
+r13 sp stack pointer
+r14 lr link register
+r15 pc program counter
+</code></pre>
+<h3><a class="header" href="#special-registers" id="special-registers">Special registers</a></h3>
+<pre><code class="language-markdown">bytes
+[3:0] desc
+---------------------------------------------
+cpsr current program status register
+</code></pre>
+<h3><a class="header" href="#cpsr-register" id="cpsr-register">CPSR register</a></h3>
+<pre><code class="language-markdown">cpsr
+bits desc
+-----------------------------
+ [31] N negative flag
+ [30] Z zero flag
+ [29] C carry flag
+ [28] V overflow flag
+ [27] Q cummulative saturation (sticky)
+ [9] E load/store endianness
+ [8] A disable asynchronous aborts
+ [7] I disable IRQ
+ [6] F disable FIQ
+ [5] T indicate Thumb state
+[4:0] M process mode (USR, FIQ, IRQ, SVC, ABT, UND, SYS)
+</code></pre>
+<h2><a class="header" href="#instructions-cheatsheet" id="instructions-cheatsheet">Instructions cheatsheet</a></h2>
+<h3><a class="header" href="#accessing-system-registers" id="accessing-system-registers">Accessing system registers</a></h3>
+<p>Reading from system registers:</p>
+<pre><code class="language-armasm">mrs r0, cpsr // move cpsr into r0
+</code></pre>
+<p>Writing to system registers:</p>
+<pre><code class="language-armasm">msr cpsr, r0 // move r0 into cpsr
+</code></pre>
+<h3><a class="header" href="#control-flow" id="control-flow">Control Flow</a></h3>
+<pre><code class="language-armasm">b &lt;lable&gt; // relative forward/back branch
+bl &lt;lable&gt; // relative forward/back branch &amp; link return addr in r14 (LR)
+
+// branch &amp; exchange (can change between ARM &amp; Thumb instruction set)
+// bit Rm[0] == 0 -&gt; ARM
+// bit Rm[0] == 1 -&gt; Thumb
+bx &lt;Rm&gt; // absolute branch to address in register Rm
+blx &lt;Rm&gt; // absolute branch to address in register Rm &amp;
+ // link return addr in r14 (LR)
+</code></pre>
+<h3><a class="header" href="#loadstore" id="loadstore">Load/Store</a></h3>
+<p>Different addressing modes.</p>
+<pre><code class="language-armasm">str r1, [r0] // [r0]=r1
+str r1, [r0, #4] // [r0+4]=r1
+str r1, [r0, #4]! // r0+=4; [r0]=r1
+str r1, [r0], 4 // [r0]=r1; r0+=4
+</code></pre>
+<p>Load/store multiple registers full-descending.</p>
+<pre><code class="language-armasm">stmfd r0!, {r1-r2, r5} // r0-=4; [r0]=r5
+ // r0-=4; [r0]=r2
+ // r0-=4; [r0]=r1
+ldmfd r0!, {r1-r2, r5} // r1=[r0]; r0+=4
+ // r2=[r0]; r0+=4
+ // r5=[r0]; r0+=4
+</code></pre>
+<blockquote>
+<p><code>!</code> is optional but has the effect to update the base pointer register <code>r0</code> here.</p>
+</blockquote>
+<p>Push/Pop</p>
+<pre><code class="language-armasm">push {r0-r2} // effectively stmfd sp!, {r0-r2}
+pop {r0-r2} // effectively ldmfd sp!, {r0-r2}
+</code></pre>
+<h2><a class="header" href="#procedure-call-standard-arm-a-hrefhttpsgithubcomarm-softwareabi-aablobmasteraapcs32aapcs32rstaapcs32a" id="procedure-call-standard-arm-a-hrefhttpsgithubcomarm-softwareabi-aablobmasteraapcs32aapcs32rstaapcs32a">Procedure Call Standard ARM (<a href="https://github.com/ARM-software/abi-aa/blob/master/aapcs32/aapcs32.rst"><code>aapcs32</code></a>)</a></h2>
+<h3><a class="header" href="#passing-arguments-to-functions" id="passing-arguments-to-functions">Passing arguments to functions</a></h3>
+<ul>
+<li>integer/pointer arguments
+<pre><code class="language-markdown">reg arg
+-----------
+r0 1
+.. ..
+r3 4
+</code></pre>
+</li>
+<li>a double word (64bit) is passed in two consecutive registers (eg <code>r1+r2</code>)</li>
+<li>additional arguments are passed on the stack. Arguments are pushed
+<code>right-to-left (RTL)</code>, meaning next arguments are closer to current <code>sp</code>.
+<pre><code class="language-markdown">void take(..., int a5, int a6);
+ | | | ... | Hi
+ | +--&gt;| a6 | |
+ +----------&gt;| a5 | &lt;-SP |
+ +-----+ v
+ | ... | Lo
+</code></pre>
+</li>
+</ul>
+<h3><a class="header" href="#return-values-from-functions" id="return-values-from-functions">Return values from functions</a></h3>
+<ul>
+<li>integer/pointer return values
+<pre><code class="language-markdown">reg size
+-----------------
+r0 32 bit
+r0+r1 64 bit
+</code></pre>
+</li>
+</ul>
+<h3><a class="header" href="#callee-saved-registers" id="callee-saved-registers">Callee saved registers</a></h3>
+<ul>
+<li><code>r4</code> - <code>r11</code></li>
+<li><code>sp</code></li>
+</ul>
+<h3><a class="header" href="#stack" id="stack">Stack</a></h3>
+<ul>
+<li>full descending
+<ul>
+<li>full: <code>sp</code> points to the last used location (valid item)</li>
+<li>descending: stack grows downwards</li>
+</ul>
+</li>
+<li><code>sp</code> must be 4byte aligned (word boundary) at all time</li>
+<li><code>sp</code> must be 8byte aligned on public interface interfaces</li>
+</ul>
+<h3><a class="header" href="#frame-chain" id="frame-chain">Frame chain</a></h3>
+<ul>
+<li>not strictly required by each platform</li>
+<li>linked list of stack-frames</li>
+<li>each frame links to the frame of its caller by a <code>frame record</code>
+<ul>
+<li>a frame record is described as a <code>(FP,LR)</code> pair (2x32bit)</li>
+</ul>
+</li>
+<li><code>r11 (FP)</code> must point to the frame record of the current stack-frame
+<pre><code class="language-markdown"> +------+ Hi
+ | 0 | frame0 |
+ +-&gt;| 0 | |
+ | | ... | |
+ | +------+ |
+ | | LR | frame1 |
+ +--| FP |&lt;-+ |
+ | ... | | |
+ +------+ | |
+ | LR | | current |
+r11 -&gt;| FP |--+ frame v
+ | ... | Lo
+</code></pre>
+</li>
+<li>end of the frame chain is indicated by following frame record <code>(0,-)</code></li>
+<li>location of the frame record in the stack frame is not specified</li>
+<li><code>r11</code> is not updated before the new frame record is fully constructed</li>
+</ul>
+<h3><a class="header" href="#function-prologue--epilogue" id="function-prologue--epilogue">Function prologue &amp; epilogue</a></h3>
+<ul>
+<li>prologue
+<pre><code class="language-armasm">push {fp, lr}
+mov fp, sp // FP points to frame record
+</code></pre>
+</li>
+<li>epilogue
+<pre><code class="language-armasm">pop {fp, pc} // pop LR directly into PC
+</code></pre>
+</li>
+</ul>
+<h2><a class="header" href="#asm-skeleton" id="asm-skeleton">ASM skeleton</a></h2>
+<p>Small assembler skeleton, ready to use with following properties:</p>
+<ul>
+<li>use raw Linux syscalls (<code>man 2 syscall</code> for ABI)</li>
+<li>no <code>C runtime (crt)</code></li>
+<li>gnu assembler <a href="https://sourceware.org/binutils/docs/as"><code>gas</code></a></li>
+</ul>
+<pre><code class="language-armasm">// file: greet.S
+
+#include &lt;asm/unistd.h&gt; // syscall NRs
+
+ .arch armv7-a
+
+ .section .text, &quot;ax&quot;
+ .balign 4
+
+ // Emit `arm` instructions, same as `.arm` directive.
+ .code 32
+ .global _start
+_start:
+ // Branch with link and exchange instruction set.
+ blx _do_greet
+
+ mov r0, #0 // exit code
+ mov r7, #__NR_exit // exit(2) syscall
+ swi 0x0
+
+ // Emit `thumb` instructions, same as `.thumb` directive.
+ .code 16
+ .thumb_func
+_do_greet:
+ mov r0, #2 // fd
+ ldr r1, =greeting // buf
+ ldr r2, =greeting_len // &amp;len
+ ldr r2, [r2] // len
+ mov r7, #__NR_write // write(2) syscall
+ swi 0x0
+
+ // Branch and exchange instruction set.
+ bx lr
+
+ .balign 8 // align data on 8byte boundary
+ .section .rodata, &quot;a&quot;
+greeting:
+ .asciz &quot;Hi ASM-World!\n&quot;
+greeting_len:
+ .int .-greeting
+</code></pre>
+<blockquote>
+<p>man gcc: <code>file.S</code> assembler code that must be preprocessed.</p>
+</blockquote>
+<p>To cross-compile and run:</p>
+<pre><code class="language-bash">&gt; arm-linux-gnueabi-gcc -o greet greet.S -nostartfiles -nostdlib \
+ -Wl,--dynamic-linker=/usr/arm-linux-gnueabi/lib/ld-linux.so.3 \
+ &amp;&amp; qemu-arm ./greet
+Hi ASM-World!
+</code></pre>
+<blockquote>
+<p>Cross-compiling on <code>Ubuntu 20.04 (x86_64)</code>, paths might differ on other
+distributions. Explicitly specifying the dynamic linker should not be
+required when compiling natively on arm.</p>
+</blockquote>
+<h2><a class="header" href="#references" id="references">References</a></h2>
+<ul>
+<li><a href="https://github.com/ARM-software/abi-aa/blob/master/aapcs32/aapcs32.rst">Procedure Call Standard ARM</a></li>
+<li><a href="https://developer.arm.com/documentation/den0013/latest">ARMv7-A Programmer's Guide</a></li>
+<li><a href="https://developer.arm.com/documentation/ddi0406/latest">ARMv7-A Architecture Reference Manual</a></li>
+<li><a href="https://sourceware.org/binutils/docs/as">GNU Assembler</a></li>
+<li><a href="https://sourceware.org/binutils/docs/as/Pseudo-Ops.html#Pseudo-Ops">GNU Assembler Directives</a></li>
+<li><a href="https://sourceware.org/binutils/docs/as/ARM_002dDependent.html">GNU Assembler <code>ARM</code> dependent features</a></li>
+</ul>
+
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