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| author | johannst <johannst@users.noreply.github.com> | 2021-06-20 22:11:42 +0000 |
|---|---|---|
| committer | johannst <johannst@users.noreply.github.com> | 2021-06-20 22:11:42 +0000 |
| commit | 7dd27f2a72395e51db76ee344ffba56279d5c6ff (patch) | |
| tree | fc08e7a7dae829716b715786b8d9ce009c515479 /arch | |
| parent | c665746d56789eba694af507429337ac54f3cd23 (diff) | |
| download | notes-7dd27f2a72395e51db76ee344ffba56279d5c6ff.tar.gz notes-7dd27f2a72395e51db76ee344ffba56279d5c6ff.zip | |
deploy: 97c6252800e020af05f0e0d7afc037c04753bc83
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/x86_64.html | 96 |
1 files changed, 78 insertions, 18 deletions
diff --git a/arch/x86_64.html b/arch/x86_64.html index 9797dd3..260b742 100644 --- a/arch/x86_64.html +++ b/arch/x86_64.html @@ -184,26 +184,31 @@ rip eip ip instruction pointer </code></pre> <h3><a class="header" href="#flags-register" id="flags-register">FLAGS register</a></h3> <pre><code class="language-markdown">rflags -bits desc ------------------------------ -[11] OF overflow flag -[10] DF direction flag - [7] SF sign flag - [6] ZF zero flag - [4] AF auxiliary carry flag - [2] PF parity flag - [0] CF carry flag +bits desc instr comment +-------------------------------------------------------------------------------------------------------------- + [21] ID identification ability to set/clear -> indicates support for CPUID instr + [18] AC alignment check alignment exception for PL 3 (user), requires CR0.AM +[13:12] IOPL io privilege level + [11] OF overflow flag + [10] DF direction flag cld/std + [9] IF interrupt enable cli/sti + [7] SF sign flag + [6] ZF zero flag + [4] AF auxiliary carry flag + [2] PF parity flag + [0] CF carry flag </code></pre> -<h2><a class="header" href="#addressing" id="addressing">Addressing</a></h2> -<pre><code class="language-asm">movw [rax], rbx // save val in rbx at [rax] -movw [imm], rbx // save val in rbx at [imm] -movw rax, [rbx+4*rcx] // load val at [rbx+4*rcx] into rax +<p>Change flag bits with <code>pushf</code> / <code>popf</code> instructions:</p> +<pre><code class="language-x86asm">pushfd // push flags (4bytes) onto stack +or dword ptr [esp], (1 << 18) // enable AC flag +popfd // pop flags (4byte) from stack </code></pre> -<p><code>rip</code> relative addressing:</p> -<pre><code class="language-asm">lea rax, [rip+.my_str] // load addr of .my_str into rax -... -.my_str: -.asciz "Foo" +<blockquote> +<p>There is also <code>pushfq</code> / <code>popfq</code> to push and pop all 8 bytes of <code>rflags</code>.</p> +</blockquote> +<h3><a class="header" href="#model-specific-register-msr" id="model-specific-register-msr">Model Specific Register (MSR)</a></h3> +<pre><code class="language-x86asm">rdmsr // Read MSR register, effectively does EDX:EAX <- MSR[ECX] +wrmsr // Write MSR register, effectively does MSR[ECX] <- EDX:EAX </code></pre> <h2><a class="header" href="#size-directives" id="size-directives">Size directives</a></h2> <p>Explicitly specify size of the operation.</p> @@ -212,6 +217,61 @@ mov word ptr [rax], 0xff // save 2 byte(s) at [rax] mov dword ptr [rax], 0xff // save 4 byte(s) at [rax] mov qword ptr [rax], 0xff // save 8 byte(s) at [rax] </code></pre> +<h2><a class="header" href="#addressing" id="addressing">Addressing</a></h2> +<pre><code class="language-x86asm">mov qword ptr [rax], rbx // save val in rbx at [rax] +mov qword ptr [imm], rbx // save val in rbx at [imm] +mov rax, qword ptr [rbx+4*rcx] // load val at [rbx+4*rcx] into rax +</code></pre> +<p><code>rip</code> relative addressing:</p> +<pre><code class="language-x86asm">lea rax, [rip+.my_str] // load addr of .my_str into rax +... +.my_str: +.asciz "Foo" +</code></pre> +<h2><a class="header" href="#string-instructions" id="string-instructions">String instructions</a></h2> +<p>The operand size of a string instruction is defined by the instruction suffix +<code>b | w | d | q</code>.</p> +<p>Source and destination registers are modified according to the <code>direction flag (DF)</code> in the <code>flags</code> register</p> +<ul> +<li><code>DF=0</code> increment src/dest registers</li> +<li><code>DF=1</code> decrement src/dest registers</li> +</ul> +<p>Following explanation assumes <code>byte</code> operands with <code>DF=0</code>:</p> +<pre><code class="language-x86asm">movsb // move data from string to string + // ES:[DI] <- DS:[SI] + // DI <- DI + 1 + // SI <- SI + 1 + +lodsb // load string + // AL <- DS:[SI] + // SI <- SI + 1 + +stosb // store string + // ES:[DI] <- AL + // DI <- DI + 1 + +cmpsb // compare string operands + // DS:[SI] - ES:[DI] ; set status flag (eg ZF) + // SI <- SI + 1 + // DI <- DI + 1 + +scasb // scan string + // AL - ES:[DI] ; set status flag (eg ZF) + // DI <- DI + 1 +</code></pre> +<p>String operations can be repeated:</p> +<pre><code class="language-x86asm">rep // repeat until rcx = 0 +repz // repeat until rcx = 0 or while ZF = 0 +repnz // repeat until rcx = 0 or while ZF = 1 +</code></pre> +<h3><a class="header" href="#example-simple-memset" id="example-simple-memset">Example: Simple <code>memset</code></a></h3> +<pre><code class="language-x86asm">// memset (dest, 0xaa /* char */, 0x10 /* len */) + +lea di, [dest] +mov al, 0xaa +mov cx, 0x10 +rep stosb +</code></pre> <h2><a class="header" href="#a-hrefhttpswwwuclibcorgdocspsabi-x86_64pdfsysv-x86_64-abia" id="a-hrefhttpswwwuclibcorgdocspsabi-x86_64pdfsysv-x86_64-abia"><a href="https://www.uclibc.org/docs/psABI-x86_64.pdf">SysV x86_64 ABI</a></a></h2> <h3><a class="header" href="#passing-arguments-to-functions" id="passing-arguments-to-functions">Passing arguments to functions</a></h3> <ul> |