From d9a14daa00e62de637c063f357c38cd86efd7666 Mon Sep 17 00:00:00 2001 From: johannst Date: Sat, 30 Apr 2022 17:43:08 +0000 Subject: deploy: f33fbacc6aaa54599458ac3eb375708650656010 --- arch/arm64.html | 2 +- arch/armv7.html | 10 +- arch/index.html | 3 +- arch/riscv.html | 292 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ arch/x86_64.html | 2 +- 5 files changed, 305 insertions(+), 4 deletions(-) create mode 100644 arch/riscv.html (limited to 'arch') diff --git a/arch/arm64.html b/arch/arm64.html index 5bac48d..2970a7d 100644 --- a/arch/arm64.html +++ b/arch/arm64.html @@ -81,7 +81,7 @@ diff --git a/arch/armv7.html b/arch/armv7.html index 134637e..de0a0ae 100644 --- a/arch/armv7.html +++ b/arch/armv7.html @@ -81,7 +81,7 @@ @@ -407,6 +407,10 @@ required when compiling natively on arm.

+ +
@@ -421,6 +425,10 @@ required when compiling natively on arm.

+ + diff --git a/arch/index.html b/arch/index.html index 007c4b5..69881e5 100644 --- a/arch/index.html +++ b/arch/index.html @@ -81,7 +81,7 @@ @@ -157,6 +157,7 @@
  • x86_64
  • arm64
  • armv7
    • +
  • riscv
    • diff --git a/arch/riscv.html b/arch/riscv.html new file mode 100644 index 0000000..2e5f697 --- /dev/null +++ b/arch/riscv.html @@ -0,0 +1,292 @@ + + + + + + riscv - Notes + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
    + +
    + + + + + + + + + + +
    +
    +

    riscv

    +

    keywords: rv32, rv64

    +
      +
    • ISA type: RISC
      • +
    • Endianness: little, big
      • +
    +

    Registers

    +
      +
    • riscv32 => XLEN=32
      • +
    • riscv64 => XLEN=64
      • +
    +

    General purpose registers

    +
    [XLEN-1:0]     abi name     desc
+---------------------------------------------
+x0             zero         zero register
+x1             ra           return addr
+x2             sp           stack ptr
+x3             gp           global ptr
+x4             tp           thread ptr
+x5-x7          t0-t2        temp regs
+x8-x9          s0-s1        saved regs
+x10-x17        a0-a7        arg regs
+x18-x27        s2-s11       saved regs
+x28-x31        t3-t6        temp regs
+
    +

    ASM skeleton

    +

    Small assembler skeleton, ready to use with following properties:

    +
      +
    • use raw Linux syscalls (man 2 syscall for ABI)
      • +
    • no C runtime (crt)
      • +
    • gnu assembler gas
      • +
    +
    // file: greet.S
+
+#include <asm/unistd.h>     // syscall NRs
+
+    .section .text, "ax", @progbits
+    .balign 4               // align code on 4byte boundary
+    .global _start
+_start:
+    li a0, 2                // fd
+    la a1, greeting         // buf
+    ld a2, (greeting_len)   // &len
+    li a7, __NR_write       // write(2) syscall
+    ecall
+
+    li a0, 42               // exit code
+    li a7, __NR_exit        // exit(2) syscall
+    ecall
+
+    .balign 8               // align data on 8byte boundary
+    .section .rodata, "a", @progbits
+greeting:
+    .asciz "Hi ASM-World!\n"
+greeting_len:
+    .int .-greeting
+
    +
    +

    man gcc: file.S assembler code that must be preprocessed.

    +
    +

    To cross-compile and run:

    +
    > riscv64-linux-gnu-gcc -o greet greet.S -nostartfiles -nostdlib                \
+    -Wl,--dynamic-linker=/usr/riscv64-linux-gnu/lib/ld-linux-riscv64-lp64d.so.1 \
+  && qemu-riscv64 ./greet
+Hi ASM-World!
+
    +
    +

    Cross-compiling on Ubuntu 20.04 (x86_64), paths might differ on other +distributions. Explicitly specifying the dynamic linker should not be +required when compiling natively on riscv.

    +

    Select dynamic linker according to abi used during compile & link.

    +
    +

    References

    + + +
    + + +
    +
    + + + +
    + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/arch/x86_64.html b/arch/x86_64.html index 0263b9b..c9a643b 100644 --- a/arch/x86_64.html +++ b/arch/x86_64.html @@ -81,7 +81,7 @@ -- cgit v1.2.3