From fe84155562f3e6d51b94155197ab5606f2e3bebe Mon Sep 17 00:00:00 2001 From: johannst Date: Sun, 28 Feb 2021 20:37:15 +0000 Subject: deploy: 5e76b1948f7d7f499993862933f0622cf76d83ff --- print.html | 256 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 252 insertions(+), 4 deletions(-) (limited to 'print.html') diff --git a/print.html b/print.html index 8464508..512c1c5 100644 --- a/print.html +++ b/print.html @@ -83,7 +83,7 @@ @@ -2359,6 +2359,7 @@ As we can see the offset from relocation at index 0 points to
  • x86_64
  • arm64
    • +
  • armv7

    • x86_64

    keywords: x86_64, x86, abi

    @@ -2565,6 +2566,7 @@ Hi ASM-World!
  • Intel 64 Vol3: System Programming Guide
  • GNU Assembler
  • GNU Assembler Directives
    • +
  • GNU Assembler x86_64 dependent features

    • arm64

    keywords: arm64, aarch64, abi

    @@ -2682,7 +2684,12 @@ x0 64 bit

    Stack

    @@ -2779,11 +2786,252 @@ required when compiling natively on arm64.

    References

    +

    armv7a

    +

    keywords: arm, armv7, abi

    + +

    Registers

    +

    General purpose registers

    +
    bytes
+[3:0]     alt     desc
+---------------------------------------------
+r0-r12            general purpose registers
+r11       fp
+r13       sp      stack pointer
+r14       lr      link register
+r15       pc      program counter
+
    +

    Special registers

    +
    bytes
+[3:0]             desc
+---------------------------------------------
+cpsr              current program status register
+
    +

    CPSR register

    +
    cpsr
+bits  desc
+-----------------------------
+ [31]  N negative flag
+ [30]  Z zero flag
+ [29]  C carry flag
+ [28]  V overflow flag
+ [27]  Q cummulative saturation (sticky)
+  [9]  E load/store endianness
+  [8]  A disable asynchronous aborts
+  [7]  I disable IRQ
+  [6]  F disable FIQ
+  [5]  T indicate Thumb state
+[4:0]  M process mode (USR, FIQ, IRQ, SVC, ABT, UND, SYS)
+
    +

    Instructions cheatsheet

    +

    Accessing system registers

    +

    Reading from system registers:

    +
    mrs r0, cpsr      // move cpsr into r0
+
    +

    Writing to system registers:

    +
    msr cpsr, r0      // move r0 into cpsr
+
    +

    Control Flow

    +
    b <lable>     // relative forward/back branch
+bl <lable>    // relative forward/back branch & link return addr in r14 (LR)
+
+// branch & exchange (can change between ARM & Thumb instruction set)
+//   bit Rm[0] == 0 -> ARM
+//   bit Rm[0] == 1 -> Thumb
+bx <Rm>       // absolute branch to address in register Rm
+blx <Rm>      // absolute branch to address in register Rm &
+              // link return addr in r14 (LR)
+
    +

    Load/Store

    +

    Different addressing modes.

    +
    str r1, [r0]         // [r0]=r1
+str r1, [r0, #4]     // [r0+4]=r1
+str r1, [r0, #4]!    // r0+=4; [r0]=r1
+str r1, [r0], 4      // [r0]=r1; r0+=4
+
    +

    Load/store multiple registers full-descending.

    +
    stmfd r0!, {r1-r2, r5}    // r0-=4; [r0]=r5
+                          // r0-=4; [r0]=r2
+                          // r0-=4; [r0]=r1
+ldmfd r0!, {r1-r2, r5}    // r1=[r0]; r0+=4
+                          // r2=[r0]; r0+=4
+                          // r5=[r0]; r0+=4
+
    +
    +

    ! is optional but has the effect to update the base pointer register r0 here.

    +
    +

    Push/Pop

    +
    push {r0-r2}    // effectively stmfd sp!, {r0-r2}
+pop {r0-r2}     // effectively ldmfd sp!, {r0-r2}
+
    +

    Procedure Call Standard ARM (aapcs32)

    +

    Passing arguments to functions

    + +

    Return values from functions

    + +

    Callee saved registers

    + +

    Stack

    + +

    Frame chain

    + +

    Function prologue & epilogue

    + +

    ASM skeleton

    +

    Small assembler skeleton, ready to use with following properties:

    + +
    // file: greet.S
+
+#include <asm/unistd.h>      // syscall NRs
+
+    .arch armv7-a
+
+    .section .text, "ax"
+    .balign 4
+
+    // Emit `arm` instructions, same as `.arm` directive.
+    .code 32
+    .global _start
+_start:
+    // Branch with link and exchange instruction set.
+    blx _do_greet
+
+    mov r0, #0               // exit code
+    mov r7, #__NR_exit       // exit(2) syscall
+    swi 0x0
+
+    // Emit `thumb` instructions, same as `.thumb` directive.
+    .code 16
+    .thumb_func
+_do_greet:
+    mov r0, #2               // fd
+    ldr r1, =greeting        // buf
+    ldr r2, =greeting_len    // &len
+    ldr r2, [r2]             // len
+    mov r7, #__NR_write      // write(2) syscall
+    swi 0x0
+
+    // Branch and exchange instruction set.
+    bx lr
+
+    .balign 8                // align data on 8byte boundary
+    .section .rodata, "a"
+greeting:
+    .asciz "Hi ASM-World!\n"
+greeting_len:
+    .int .-greeting
+
    +
    +

    man gcc: file.S assembler code that must be preprocessed.

    +
    +

    To cross-compile and run:

    +
    > arm-linux-gnueabi-gcc -o greet greet.S -nostartfiles -nostdlib  \
+    -Wl,--dynamic-linker=/usr/arm-linux-gnueabi/lib/ld-linux.so.3 \
+  && qemu-arm ./greet
+Hi ASM-World!
+
    +
    +

    Cross-compiling on Ubuntu 20.04 (x86_64), paths might differ on other +distributions. Explicitly specifying the dynamic linker should not be +required when compiling natively on arm.

    +
    +

    References

    + -- cgit v1.2.3