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<h1 class="menu-title">Notes</h1>
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<h1 id="x86_64"><a class="header" href="#x86_64">x86_64</a></h1>
<p>keywords: x86_64, x86, abi</p>
<ul>
<li>64bit synonyms: <code>x86_64</code>, <code>x64</code>, <code>amd64</code>, <code>intel 64</code></li>
<li>32bit synonyms: <code>x86</code>, <code>ia32</code>, <code>i386</code></li>
<li>ISA type: <code>CISC</code></li>
<li>Endianness: <code>little</code></li>
</ul>
<h2 id="registers"><a class="header" href="#registers">Registers</a></h2>
<h3 id="general-purpose-register"><a class="header" href="#general-purpose-register">General purpose register</a></h3>
<pre><code class="language-markdown">bytes
[7:0] [3:0] [1:0] [1] [0] desc
----------------------------------------------------------
rax eax ax ah al accumulator
rbx ebx bx bh bl base register
rcx ecx cx ch cl counter
rdx edx dx dh dl data register
rsi esi si - sil source index
rdi edi di - dil destination index
rbp ebp bp - bpl base pointer
rsp esp sp - spl stack pointer
r8-15 rNd rNw - rNb
</code></pre>
<h3 id="special-register"><a class="header" href="#special-register">Special register</a></h3>
<pre><code class="language-markdown">bytes
[7:0] [3:0] [1:0] desc
---------------------------------------------------
rflags eflags flags flags register
rip eip ip instruction pointer
</code></pre>
<h3 id="flags-register"><a class="header" href="#flags-register">FLAGS register</a></h3>
<pre><code class="language-markdown">rflags
bits desc instr comment
--------------------------------------------------------------------------------------------------------------
[21] ID identification ability to set/clear -> indicates support for CPUID instr
[18] AC alignment check alignment exception for PL 3 (user), requires CR0.AM
[13:12] IOPL io privilege level
[11] OF overflow flag
[10] DF direction flag cld/std increment (0) or decrement (1) registers in string operations
[9] IF interrupt enable cli/sti
[7] SF sign flag
[6] ZF zero flag
[4] AF auxiliary carry flag
[2] PF parity flag
[0] CF carry flag
</code></pre>
<p>Change flag bits with <code>pushf</code> / <code>popf</code> instructions:</p>
<pre><code class="language-x86asm">pushfd // push flags (4bytes) onto stack
or dword ptr [esp], (1 << 18) // enable AC flag
popfd // pop flags (4byte) from stack
</code></pre>
<blockquote>
<p>There is also <code>pushfq</code> / <code>popfq</code> to push and pop all 8 bytes of <code>rflags</code>.</p>
</blockquote>
<h3 id="model-specific-register-msr"><a class="header" href="#model-specific-register-msr">Model Specific Register (MSR)</a></h3>
<pre><code class="language-x86asm">rdmsr // Read MSR register, effectively does EDX:EAX <- MSR[ECX]
wrmsr // Write MSR register, effectively does MSR[ECX] <- EDX:EAX
</code></pre>
<h2 id="size-directives"><a class="header" href="#size-directives">Size directives</a></h2>
<p>Explicitly specify size of the operation.</p>
<pre><code class="language-x86asm">mov byte ptr [rax], 0xff // save 1 byte(s) at [rax]
mov word ptr [rax], 0xff // save 2 byte(s) at [rax]
mov dword ptr [rax], 0xff // save 4 byte(s) at [rax]
mov qword ptr [rax], 0xff // save 8 byte(s) at [rax]
</code></pre>
<h2 id="addressing"><a class="header" href="#addressing">Addressing</a></h2>
<pre><code class="language-x86asm">mov qword ptr [rax], rbx // save val in rbx at [rax]
mov qword ptr [imm], rbx // save val in rbx at [imm]
mov rax, qword ptr [rbx+4*rcx] // load val at [rbx+4*rcx] into rax
</code></pre>
<p><code>rip</code> relative addressing:</p>
<pre><code class="language-x86asm">lea rax, [rip+.my_str] // load addr of .my_str into rax
...
.my_str:
.asciz "Foo"
</code></pre>
<p>Load effective address:</p>
<pre><code class="language-x86asm">mov rax, 2
lea r11, [rax + 3] // r11 <- 5
</code></pre>
<h2 id="string-instructions"><a class="header" href="#string-instructions">String instructions</a></h2>
<p>The operand size of a string instruction is defined by the instruction suffix
<code>b | w | d | q</code>.</p>
<p>Source and destination registers are modified according to the <code>direction flag (DF)</code> in the <code>flags</code> register</p>
<ul>
<li><code>DF=0</code> increment src/dest registers</li>
<li><code>DF=1</code> decrement src/dest registers</li>
</ul>
<p>Following explanation assumes <code>byte</code> operands with <code>DF=0</code>:</p>
<pre><code class="language-x86asm">movsb // move data from string to string
// ES:[DI] <- DS:[SI]
// DI <- DI + 1
// SI <- SI + 1
lodsb // load string
// AL <- DS:[SI]
// SI <- SI + 1
stosb // store string
// ES:[DI] <- AL
// DI <- DI + 1
cmpsb // compare string operands
// DS:[SI] - ES:[DI] ; set status flag (eg ZF)
// SI <- SI + 1
// DI <- DI + 1
scasb // scan string
// AL - ES:[DI] ; set status flag (eg ZF)
// DI <- DI + 1
</code></pre>
<p>String operations can be repeated:</p>
<pre><code class="language-x86asm">rep // repeat until rcx = 0
repz // repeat until rcx = 0 or while ZF = 0
repnz // repeat until rcx = 0 or while ZF = 1
</code></pre>
<h3 id="example-simple-memset"><a class="header" href="#example-simple-memset">Example: Simple <code>memset</code></a></h3>
<pre><code class="language-x86asm">// memset (dest, 0xaa /* char */, 0x10 /* len */)
lea di, [dest]
mov al, 0xaa
mov cx, 0x10
rep stosb
</code></pre>
<h2 id="time-stamp-counter---rdtsc"><a class="header" href="#time-stamp-counter---rdtsc">Time stamp counter - <code>rdtsc</code></a></h2>
<pre><code class="language-c">static inline uint64_t rdtsc() {
uint32_t eax, edx;
asm volatile("rdtsc" : "=d"(edx), "=a"(eax)::);
return (uint64_t)edx << 32 | eax;
}
</code></pre>
<blockquote>
<p>Constant TSC behavior ensures that the duration of each clock tick is uniform
and supports the use of the TSC as a wall clock timer even if the processor
core changes frequency. This is the architectural behavior moving forward.</p>
<ul>
<li>18.17 TIME-STAMP COUNTER - <a href="https://software.intel.com/content/www/us/en/develop/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide.html">intel64-vol3</a></li>
</ul>
</blockquote>
<p>On linux one can check the <code>constant_tsc</code> cpu flag, to validate if the
implemented TSC ticks with a constant frequency.</p>
<pre><code class="language-sh">grep constant_tsc /proc/cpuinfo
</code></pre>
<h2 id="sysv-x86_64-abi"><a class="header" href="#sysv-x86_64-abi"><a href="https://gitlab.com/x86-psABIs/x86-64-ABI">SysV x86_64 ABI</a></a></h2>
<h3 id="passing-arguments-to-functions"><a class="header" href="#passing-arguments-to-functions">Passing arguments to functions</a></h3>
<ul>
<li>Integer/Pointer arguments
<pre><code class="language-markdown">reg arg
-----------
rdi 1
rsi 2
rdx 3
rcx 4
r8 5
r9 6
</code></pre>
</li>
<li>Floating point arguments
<pre><code class="language-markdown">reg arg
-----------
xmm0 1
.. ..
xmm7 8
</code></pre>
</li>
<li>Additional arguments are passed on the stack. Arguments are pushed
right-to-left (RTL), meaning next arguments are closer to current <code>rsp</code>.</li>
</ul>
<h3 id="return-values-from-functions"><a class="header" href="#return-values-from-functions">Return values from functions</a></h3>
<ul>
<li>Integer/Pointer return values
<pre><code class="language-markdown">reg size
-----------------
rax 64 bit
rax+rdx 128 bit
</code></pre>
</li>
<li>Floating point return values
<pre><code class="language-markdown">reg size
-------------------
xmm0 64 bit
xmm0+xmm1 128 bit
</code></pre>
</li>
</ul>
<h3 id="caller-saved-registers"><a class="header" href="#caller-saved-registers">Caller saved registers</a></h3>
<p>Caller must save these registers if they should be preserved across function
calls.</p>
<ul>
<li><code>rax</code></li>
<li><code>rcx</code></li>
<li><code>rdx</code></li>
<li><code>rsi</code></li>
<li><code>rdi</code></li>
<li><code>rsp</code></li>
<li><code>r8</code> - <code>r11</code></li>
</ul>
<h3 id="callee-saved-registers"><a class="header" href="#callee-saved-registers">Callee saved registers</a></h3>
<p>Caller can expect these registers to be preserved across function calls. Callee
must must save these registers in case they are used.</p>
<ul>
<li><code>rbx</code></li>
<li><code>rbp</code></li>
<li><code>r12</code> – <code>r15</code></li>
</ul>
<h3 id="stack"><a class="header" href="#stack">Stack</a></h3>
<ul>
<li>grows downwards</li>
<li>frames aligned on 16 byte boundary
<pre><code class="language-text">Hi ADDR
| +------------+
| | prev frame |
| +------------+ <--- 16 byte aligned (X & ~0xf)
| [rbp+8] | saved RIP |
| [rbp] | saved RBP |
| [rbp-8] | func stack |
| | ... |
v +------------+
Lo ADDR
</code></pre>
</li>
</ul>
<h3 id="function-prologue--epilogue"><a class="header" href="#function-prologue--epilogue">Function prologue & epilogue</a></h3>
<ul>
<li>prologue
<pre><code class="language-x86asm">push rbp // save caller base pointer
mov rbp, rsp // save caller stack pointer
</code></pre>
</li>
<li>epilogue
<pre><code class="language-x86asm">mov rsp, rbp // restore caller stack pointer
pop rbp // restore caller base pointer
</code></pre>
<blockquote>
<p>Equivalent to <code>leave</code> instruction.</p>
</blockquote>
</li>
</ul>
<h2 id="windows-x64-abi"><a class="header" href="#windows-x64-abi"><a href="https://learn.microsoft.com/en-us/cpp/build/x64-software-conventions">Windows x64 ABI</a></a></h2>
<h3 id="passing-arguments-to-functions-ref"><a class="header" href="#passing-arguments-to-functions-ref">Passing arguments to functions (<a href="https://learn.microsoft.com/en-us/cpp/build/x64-calling-convention">ref</a>)</a></h3>
<blockquote>
<p>A single argument is never spread across multiple registers.</p>
</blockquote>
<ul>
<li>Integer/Pointer arguments
<pre><code class="language-markdown">reg arg
-----------
rcx 1
rdx 2
r8 3
r9 4
</code></pre>
</li>
<li>Floating point arguments
<pre><code class="language-markdown">reg arg
-----------
xmm0 1
.. ..
xmm3 4
</code></pre>
</li>
<li>Additional arguments are passed on the stack. Arguments are pushed
right-to-left (RTL), meaning next arguments are closer to current <code>rsp</code>.
<a href="https://godbolt.org/z/oT5Tjdf7Y">See example</a>.</li>
</ul>
<h3 id="return-values-from-functions-1"><a class="header" href="#return-values-from-functions-1">Return values from functions</a></h3>
<ul>
<li>Integer/Pointer return values
<pre><code class="language-markdown">reg size
-----------------
rax 64 bit
</code></pre>
</li>
<li>Floating point return values
<pre><code class="language-markdown">reg size
-------------------
xmm0 64 bit
</code></pre>
</li>
</ul>
<h3 id="caller-saved-registers-1"><a class="header" href="#caller-saved-registers-1">Caller saved registers</a></h3>
<p>Caller must save these registers if they should be preserved across function
calls.</p>
<ul>
<li><code>rax</code></li>
<li><code>rcx</code></li>
<li><code>rdx</code></li>
<li><code>r8</code> - <code>r11</code></li>
<li><code>xmm0</code> - <code>xmm5</code></li>
</ul>
<h3 id="callee-saved-registers-1"><a class="header" href="#callee-saved-registers-1">Callee saved registers</a></h3>
<p>Caller can expect these registers to be preserved across function calls. Callee
must must save these registers in case they are used.</p>
<ul>
<li><code>rbx</code></li>
<li><code>rbp</code></li>
<li><code>rdi</code></li>
<li><code>rsi</code></li>
<li><code>rsp</code></li>
<li><code>r12</code> - <code>r15</code></li>
<li><code>xmm6</code> - <code>xmm15</code></li>
</ul>
<h2 id="asm-skeleton"><a class="header" href="#asm-skeleton">ASM skeleton</a></h2>
<p>Small assembler skeleton, ready to use with following properties:</p>
<ul>
<li>use raw Linux syscalls (<code>man 2 syscall</code> for ABI)</li>
<li>no <code>C runtime (crt)</code></li>
<li>gnu assembler <a href="https://sourceware.org/binutils/docs/as"><code>gas</code></a></li>
<li>intel syntax</li>
</ul>
<pre><code class="language-x86asm"># file: greet.s
.intel_syntax noprefix
.section .text, "ax", @progbits
.global _start
_start:
mov rdi, 1 # fd
lea rsi, [rip + greeting] # buf
mov rdx, [rip + greeting_len] # count
mov rax, 1 # write(2) syscall nr
syscall
mov rdi, 0 # exit code
mov rax, 60 # exit(2) syscall nr
syscall
.section .rdonly, "a", @progbits
greeting:
.asciz "Hi ASM-World!\n"
greeting_len:
.int .-greeting
</code></pre>
<blockquote>
<p>Syscall numbers are defined in <code>/usr/include/asm/unistd.h</code>.</p>
</blockquote>
<p>To compile and run:</p>
<pre><code class="language-bash">> gcc -o greet greet.s -nostartfiles -nostdlib && ./greet
Hi ASM-World!
</code></pre>
<h2 id="references"><a class="header" href="#references">References</a></h2>
<ul>
<li><a href="https://gitlab.com/x86-psABIs/x86-64-ABI">SystemV AMD64 ABI</a></li>
<li><a href="https://www.amd.com/system/files/TechDocs/24592.pdf">AMD64 Vol1: Application Programming</a></li>
<li><a href="https://www.amd.com/system/files/TechDocs/24593.pdf">AMD64 Vol2: System Programming</a></li>
<li><a href="https://www.amd.com/system/files/TechDocs/24594.pdf">AMD64 Vol3: General-Purpose & System Instructions</a></li>
<li><a href="https://cs.brown.edu/courses/cs033/docs/guides/x64_cheatsheet.pdf">X86_64 Cheat-Sheet</a></li>
<li><a href="https://software.intel.com/content/www/us/en/develop/download/intel-64-and-ia-32-architectures-software-developers-manual-volume-1-basic-architecture.html">Intel 64 Vol1: Basic Architecture</a></li>
<li><a href="https://software.intel.com/content/www/us/en/develop/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-2a-2b-2c-and-2d-instruction-set-reference-a-z.html">Intel 64 Vol2: Instruction Set Reference</a></li>
<li><a href="https://software.intel.com/content/www/us/en/develop/download/intel-64-and-ia-32-architectures-sdm-combined-volumes-3a-3b-3c-and-3d-system-programming-guide.html">Intel 64 Vol3: System Programming Guide</a></li>
<li><a href="https://sourceware.org/binutils/docs/as">GNU Assembler</a></li>
<li><a href="https://sourceware.org/binutils/docs/as/Pseudo-Ops.html#Pseudo-Ops">GNU Assembler Directives</a></li>
<li><a href="https://sourceware.org/binutils/docs/as/i386_002dDependent.html">GNU Assembler <code>x86_64</code> dependent features</a></li>
<li><a href="https://github.com/johannst/juicebox-asm"><code>juicebox-asm</code> an <code>x86_64</code> jit assembler playground</a></li>
</ul>
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