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authorJohannes Stoelp <johannes.stoelp@gmail.com>2024-03-18 21:48:56 +0100
committerJohannes Stoelp <johannes.stoelp@gmail.com>2024-03-18 21:48:56 +0100
commite931314b97a698d0bb24cbf7c1d9de01f5dbb899 (patch)
tree187993858dc69255a8f0802f0fc196628c7f209a /roles/webserver/files/www/memzero/pub/references.html
parent8ca26cbb43f8ff2b0b5a2c49d8e11a2f4dd54b79 (diff)
downloadansible-memzero-e931314b97a698d0bb24cbf7c1d9de01f5dbb899.tar.gz
ansible-memzero-e931314b97a698d0bb24cbf7c1d9de01f5dbb899.zip
nginx: add riscv pub/ docs
Diffstat (limited to 'roles/webserver/files/www/memzero/pub/references.html')
-rw-r--r--roles/webserver/files/www/memzero/pub/references.html14
1 files changed, 13 insertions, 1 deletions
diff --git a/roles/webserver/files/www/memzero/pub/references.html b/roles/webserver/files/www/memzero/pub/references.html
index 1f7c71e..dbc7018 100644
--- a/roles/webserver/files/www/memzero/pub/references.html
+++ b/roles/webserver/files/www/memzero/pub/references.html
@@ -42,7 +42,7 @@
const filter = document.getElementById("filter");
// Create buttons for each tag T.
- ["clear", "sysv", "arm", "x86"].forEach(T => {
+ ["clear", "sysv", "arm", "x86", "riscv"].forEach(T => {
const btn = document.createElement("button");
btn.innerHTML = T;
btn.onclick = T === "clear"
@@ -83,6 +83,10 @@
<a style="color:black;" href="/pub/abi/arm/aapcs64.pdf">abi/arm/aapcs64.pdf</a>
[<a href="https://github.com/ARM-software/abi-aa/releases/download/2023Q3/aapcs64.pdf">original</a>]
</li>
+ <li class="content syss riscv">
+ <a style="color:black;" href="/pub/abi/sysv/sysv-psabi-riscv.pdf">abi/sysv/sysv-psabi-riscv.pdf</a>
+ [<a href="https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/latest">original</a>]
+ </li>
<li class="content x86">
<a style="color:black;" href="/pub/arch/intel/intel64-optimization-ref-vol1.pdf">arch/intel/intel64-optimization-ref-vol1.pdf</a>
[<a href="https://cdrdv2.intel.com/v1/dl/getContent/671488">original</a>]
@@ -103,6 +107,14 @@
<a style="color:black;" href="/pub/arch/intel/intel64-vol3-system-programming.pdf">arch/intel/intel64-vol3-system-programming.pdf</a>
[<a href="https://cdrdv2.intel.com/v1/dl/getContent/671447">original</a>]
</li>
+ <li class="content riscv">
+ <a style="color:black;" href="/pub/arch/riscv/rv-1-unprivileged-isa.pdf">arch/riscv/rv-1-unprivileged-isa.pdf</a>
+ [<a href="https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC">original</a>]
+ </li>
+ <li class="content riscv">
+ <a style="color:black;" href="/pub/arch/riscv/rv-2-privileged-architecture.pdf">arch/riscv/rv-2-privileged-architecture.pdf</a>
+ [<a href="https://github.com/riscv/riscv-isa-manual/releases/tag/Priv-v1.12">original</a>]
+ </li>
</ul>
</body>
</html>