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authorJohannes Stoelp <johannes.stoelp@gmail.com>2023-02-27 20:32:32 +0100
committerJohannes Stoelp <johannes.stoelp@gmail.com>2023-02-27 20:32:32 +0100
commit7c080806361e23e2e2a528fb391d6bf9c15404f0 (patch)
tree2ac0d7e4bf0937a9f47bcc08ff9b8a79e8ff2833 /src/lib.rs
parentf2f0a8eb4795342a985c49d66eeda73d059e6033 (diff)
downloadjuicebox-asm-7c080806361e23e2e2a528fb391d6bf9c15404f0.tar.gz
juicebox-asm-7c080806361e23e2e2a528fb391d6bf9c15404f0.zip
Add MOV tests
Diffstat (limited to 'src/lib.rs')
-rw-r--r--src/lib.rs43
1 files changed, 41 insertions, 2 deletions
diff --git a/src/lib.rs b/src/lib.rs
index 35f7919..23c9ca0 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -24,7 +24,8 @@ impl MemOp {
}
/// Encode the `REX` byte.
-const fn rex(w: u8, r: u8, x: u8, b: u8) -> u8 {
+const fn rex(w: bool, r: u8, x: u8, b: u8) -> u8 {
+ let w = if w { 1 } else { 0 };
let r = (r >> 3) & 1;
let x = (x >> 3) & 1;
let b = (b >> 3) & 1;
@@ -227,7 +228,7 @@ trait EncodeMR<T: Reg> {
}
fn rex(op1: &MemOp, op2: T) -> Option<u8> {
- if op1.base().need_rex() || op2.need_rex() {
+ if op2.need_rex() || (op1.base().is_ext()) {
Some(rex(op2.rexw(), op2.idx(), 0, op1.base().idx()))
} else {
None
@@ -235,11 +236,19 @@ trait EncodeMR<T: Reg> {
}
}
+impl EncodeMR<Reg8> for Asm {}
+impl EncodeMR<Reg16> for Asm {
+ fn legacy_prefix() -> Option<u8> {
+ Some(0x66)
+ }
+}
impl EncodeMR<Reg32> for Asm {}
impl EncodeMR<Reg64> for Asm {}
// -- Instruction implementations.
+// -- MOV : reg reg
+
impl Mov<Reg64, Reg64> for Asm {
fn mov(&mut self, op1: Reg64, op2: Reg64) {
self.encode_rr(0x89, op1, op2);
@@ -264,6 +273,8 @@ impl Mov<Reg8, Reg8> for Asm {
}
}
+// -- MOV : mem reg
+
impl Mov<MemOp, Reg64> for Asm {
fn mov(&mut self, op1: MemOp, op2: Reg64) {
self.encode_mr(0x89, op1, op2);
@@ -276,6 +287,20 @@ impl Mov<MemOp, Reg32> for Asm {
}
}
+impl Mov<MemOp, Reg16> for Asm {
+ fn mov(&mut self, op1: MemOp, op2: Reg16) {
+ self.encode_mr(0x89, op1, op2);
+ }
+}
+
+impl Mov<MemOp, Reg8> for Asm {
+ fn mov(&mut self, op1: MemOp, op2: Reg8) {
+ self.encode_mr(0x88, op1, op2);
+ }
+}
+
+// -- MOV : reg mem
+
impl Mov<Reg64, MemOp> for Asm {
fn mov(&mut self, op1: Reg64, op2: MemOp) {
self.encode_rm(0x8b, op1, op2);
@@ -288,6 +313,20 @@ impl Mov<Reg32, MemOp> for Asm {
}
}
+impl Mov<Reg16, MemOp> for Asm {
+ fn mov(&mut self, op1: Reg16, op2: MemOp) {
+ self.encode_rm(0x8b, op1, op2);
+ }
+}
+
+impl Mov<Reg8, MemOp> for Asm {
+ fn mov(&mut self, op1: Reg8, op2: MemOp) {
+ self.encode_rm(0x8a, op1, op2);
+ }
+}
+
+// -- MOV : reg imm
+
impl Mov<Reg64, Imm64> for Asm {
fn mov(&mut self, op1: Reg64, op2: Imm64) {
self.encode_oi(0xb8, op1, op2);