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| author | johannst <johannst@users.noreply.github.com> | 2023-12-05 22:08:06 +0000 |
|---|---|---|
| committer | johannst <johannst@users.noreply.github.com> | 2023-12-05 22:08:06 +0000 |
| commit | 2294180c3778d0fcfa877818e98c420fcd54bb8a (patch) | |
| tree | 8240452d6b80d397f1b5a9425c1a986c20e710e5 /src/tiny_vm/tiny_vm.rs.html | |
| parent | e37c8e0f9319e3df3ff801f5a38f4717a8a20b28 (diff) | |
| download | juicebox-asm-2294180c3778d0fcfa877818e98c420fcd54bb8a.tar.gz juicebox-asm-2294180c3778d0fcfa877818e98c420fcd54bb8a.zip | |
deploy: 7e98f5def5942969f97f5f015e7fb8417793d132
Diffstat (limited to 'src/tiny_vm/tiny_vm.rs.html')
| -rw-r--r-- | src/tiny_vm/tiny_vm.rs.html | 1395 |
1 files changed, 1395 insertions, 0 deletions
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TinyVm example. +//! +//! This example introduces as simple 16 bit virtual machine the [`TinyVm`]. The VM consits of +//! three registers defined in [`TinyReg`], a separate _data_ and _insutrction_ memory and a small +//! set of instructions [`TinyInsn`], sufficient to implement a guest program to compute the +//! fiibonacci sequence. +//! +//! The `TinyVm` implements a simple _just-in-time (JIT)_ compiler to demonstrate the +//! [`juicebox_asm`] crate. Additionally, it implements a reference _interpreter_. +//! +//! ``` +//! fn main() { +//! let mut prog = Vec::new(); +//! prog.push(TinyInsn::LoadImm(TinyReg::A, 100)); +//! prog.push(TinyInsn::Add(TinyReg::B, TinyReg::A)); +//! prog.push(TinyInsn::Addi(TinyReg::C, 100)); +//! prog.push(TinyInsn::Halt); +//! +//! let mut vm = TinyVm::new(prog); +//! vm.interp(); +//! +//! assert_eq!(100, vm.read_reg(TinyReg::A)); +//! assert_eq!(100, vm.read_reg(TinyReg::B)); +//! assert_eq!(100, vm.read_reg(TinyReg::C)); +//! assert_eq!(4, vm.icnt); +//! assert_eq!(4, vm.pc); +//! +//! vm.pc = 0; +//! vm.jit(); +//! +//! assert_eq!(100, vm.read_reg(TinyReg::A)); +//! assert_eq!(200, vm.read_reg(TinyReg::B)); +//! assert_eq!(200, vm.read_reg(TinyReg::C)); +//! assert_eq!(8, vm.icnt); +//! assert_eq!(4, vm.pc); +//! } +//! ``` + +</span><span class="attr">#[cfg(not(any(target_arch = <span class="string">"x86_64"</span>, target_os = <span class="string">"linux"</span>)))] +</span><span class="macro">compile_error!</span>(<span class="string">"Only supported on x86_64 with SystemV abi"</span>); + +<span class="kw">use </span>juicebox_asm::prelude::<span class="kw-2">*</span>; +<span class="kw">use </span>juicebox_asm::Runtime; + +<span class="doccomment">/// A guest physical address. +</span><span class="kw">pub struct </span>PhysAddr(<span class="kw">pub </span>u16); + +<span class="kw">impl </span>Into<usize> <span class="kw">for </span>PhysAddr { + <span class="kw">fn </span>into(<span class="self">self</span>) -> usize { + <span class="self">self</span>.<span class="number">0 </span><span class="kw">as </span>usize + } +} + +<span class="doccomment">/// The registers for the [`TinyVm`]. +</span><span class="attr">#[derive(Debug, PartialEq, Clone, Copy)] +</span><span class="kw">pub enum </span>TinyReg { + A, + B, + C, +} + +<span class="kw">impl </span>TinyReg { + <span class="attr">#[inline] + </span><span class="kw">fn </span>idx(<span class="kw-2">&</span><span class="self">self</span>) -> usize { + <span class="kw-2">*</span><span class="self">self </span><span class="kw">as </span>usize + } +} + +<span class="doccomment">/// The instructions for the [`TinyVm`]. +</span><span class="attr">#[derive(Debug, PartialEq, Clone, Copy)] +</span><span class="kw">pub enum </span>TinyInsn { + <span class="doccomment">/// Halt the VM. + </span>Halt, + <span class="doccomment">/// Load the immediate value into the register `reg = imm`. + </span>LoadImm(TinyReg, u16), + <span class="doccomment">/// Load a value from the memory (absolute addressing) into the register `reg = mem[imm]`. + </span>Load(TinyReg, u16), + <span class="doccomment">/// Store a value from the register into the memory (absolute addressing) `mem[imm] = reg`. + </span>Store(TinyReg, u16), + <span class="doccomment">/// Add the register to the register `reg1 += reg2`. + </span>Add(TinyReg, TinyReg), + <span class="doccomment">/// Add the immediate to the register `reg += imm`. + </span>Addi(TinyReg, i16), + <span class="doccomment">/// Jump unconditional (absolute addressing) `pc = disp`. + </span>Branch(usize), + <span class="doccomment">/// Jump if the register is zero (absolute addressing) `pc = (reg == 0) ? disp : pc++`. + </span>BranchZero(TinyReg, usize), +} + +<span class="doccomment">/// Value returned from a [`JitFn`]. +</span><span class="attr">#[repr(C)] +</span><span class="kw">struct </span>JitRet(u64, u64); + +<span class="doccomment">/// Function signature defining the simple JIT ABI used in this example. +/// A `JitFn` represents the entry point to a jit compiled _basic block_ of the guest software. +/// +/// ```text +/// JIT entry: +/// arg0: pointer to guest registers +/// arg1: pointer to guest data memory +/// +/// JIT exit: +/// JitRet(0, N): Halt instruction, executed N instructions. +/// JitRet(N, R): N!=0 +/// End of basic block, executed N instructions, +/// must re-enter at `pc = R`. +/// ``` +</span><span class="kw">type </span>JitFn = <span class="kw">extern </span><span class="string">"C" </span><span class="kw">fn</span>(<span class="kw-2">*mut </span>u16, <span class="kw-2">*mut </span>u8) -> JitRet; + +<span class="doccomment">/// The `TinyVm` virtual machine state. +</span><span class="kw">pub struct </span>TinyVm { + <span class="doccomment">/// Data memory, covering full 16 bit guest address space. + /// + /// For simplicity add additional trailing 1 byte to support an unaligned access to 0xffff + /// without any special handling. + </span>dmem: [u8; <span class="number">0x1_0000 </span>+ <span class="number">1</span>], + <span class="doccomment">/// Instruction memory. + </span>imem: Vec<TinyInsn>, + <span class="doccomment">/// VM registers. + </span>regs: [u16; <span class="number">3</span>], + <span class="doccomment">/// VM program counter. + </span>pc: usize, + <span class="doccomment">/// VM executed instruction counter (perf counter). + </span>icnt: usize, + + <span class="comment">// -- JIT state. + </span><span class="doccomment">/// Mapping of guest PCs to jitted host code (`JitFn`). This mapping is filled when guest + /// _basic blocks_ are jitted. + </span>jit_cache: Vec<<span class="prelude-ty">Option</span><JitFn>>, + <span class="doccomment">/// JIT runtime maintaining the host pages containing the jitted guest code. + </span>rt: Runtime, +} + +<span class="kw">impl </span>TinyVm { + <span class="doccomment">/// Create a new [`TinyVm`] and initialize the instruction memory from `code`. + </span><span class="kw">pub fn </span>new(code: Vec<TinyInsn>) -> <span class="self">Self </span>{ + <span class="kw">let </span><span class="kw-2">mut </span>jit_cache = Vec::with_capacity(code.len()); + jit_cache.resize(code.len(), <span class="prelude-val">None</span>); + + TinyVm { + dmem: [<span class="number">0</span>; <span class="number">0x1_0000 </span>+ <span class="number">1</span>], + imem: code, + regs: [<span class="number">0</span>; <span class="number">3</span>], + pc: <span class="number">0</span>, + icnt: <span class="number">0</span>, + <span class="comment">// -- JIT state. + </span>jit_cache, + rt: Runtime::new(), + } + } + + <span class="doccomment">/// Read guest register. + </span><span class="attr">#[inline] + </span><span class="kw">pub fn </span>read_reg(<span class="kw-2">&</span><span class="self">self</span>, reg: TinyReg) -> u16 { + <span class="self">self</span>.regs[reg.idx()] + } + + <span class="doccomment">/// Write guest register. + </span><span class="attr">#[inline] + </span><span class="kw">pub fn </span>write_reg(<span class="kw-2">&mut </span><span class="self">self</span>, reg: TinyReg, val: u16) { + <span class="self">self</span>.regs[reg.idx()] = val; + } + + <span class="doccomment">/// Read guest data memory. + </span><span class="attr">#[inline] + </span><span class="kw">pub fn </span>read_mem(<span class="kw-2">&</span><span class="self">self</span>, paddr: PhysAddr) -> u16 { + <span class="comment">// dmem covers whole 16 bit address space + 1 byte for unaligned access at 0xffff. + </span><span class="kw">let </span>bytes = <span class="self">self</span>.dmem[paddr.into()..][..<span class="number">2</span>].try_into().unwrap(); + u16::from_le_bytes(bytes) + } + + <span class="doccomment">/// Write guest data memory. + </span><span class="attr">#[inline] + </span><span class="kw">pub fn </span>write_mem(<span class="kw-2">&mut </span><span class="self">self</span>, paddr: PhysAddr, val: u16) { + <span class="kw">let </span>bytes = val.to_le_bytes(); + <span class="self">self</span>.dmem[paddr.into()..][..<span class="number">2</span>].copy_from_slice(<span class="kw-2">&</span>bytes); + } + + <span class="doccomment">/// Dump the VM state to stdout. + </span><span class="kw">pub fn </span>dump(<span class="kw-2">&</span><span class="self">self</span>) { + <span class="macro">println!</span>(<span class="string">"-- TinyVm state --"</span>); + <span class="macro">println!</span>(<span class="string">" ICNT: {}"</span>, <span class="self">self</span>.icnt); + <span class="macro">println!</span>(<span class="string">" PC : {:02x}"</span>, <span class="self">self</span>.pc - <span class="number">1</span>); + <span class="macro">println!</span>( + <span class="string">" A:{:04x} B:{:04x} C:{:04x}"</span>, + <span class="self">self</span>.read_reg(TinyReg::A), + <span class="self">self</span>.read_reg(TinyReg::B), + <span class="self">self</span>.read_reg(TinyReg::C), + ); + } + + <span class="doccomment">/// Run in interpreter mode until the next [`TinyInsn::Halt`] instruction is hit. + </span><span class="kw">pub fn </span>interp(<span class="kw-2">&mut </span><span class="self">self</span>) { + <span class="lifetime">'outer</span>: <span class="kw">loop </span>{ + <span class="kw">let </span>insn = <span class="self">self</span>.imem[<span class="self">self</span>.pc]; + <span class="comment">//println!("[0x{:02x}] {:?}", self.pc, insn); + + </span><span class="self">self</span>.pc = <span class="self">self</span>.pc.wrapping_add(<span class="number">1</span>); + <span class="self">self</span>.icnt += <span class="number">1</span>; + + <span class="kw">match </span>insn { + TinyInsn::Halt => { + <span class="kw">break </span><span class="lifetime">'outer</span>; + } + TinyInsn::LoadImm(a, imm) => { + <span class="self">self</span>.write_reg(a, imm); + } + TinyInsn::Load(a, addr) => { + <span class="kw">let </span>val = <span class="self">self</span>.read_mem(PhysAddr(addr)); + <span class="self">self</span>.write_reg(a, val); + } + TinyInsn::Store(a, addr) => { + <span class="kw">let </span>val = <span class="self">self</span>.read_reg(a); + <span class="self">self</span>.write_mem(PhysAddr(addr), val); + } + TinyInsn::Add(a, b) => { + <span class="kw">let </span>res = <span class="self">self</span>.read_reg(a).wrapping_add(<span class="self">self</span>.read_reg(b)); + <span class="self">self</span>.write_reg(a, res); + } + TinyInsn::Addi(a, imm) => { + <span class="kw">let </span>res = <span class="self">self</span>.read_reg(a).wrapping_add(imm <span class="kw">as </span>u16); + <span class="self">self</span>.write_reg(a, res); + } + TinyInsn::Branch(disp) => { + <span class="self">self</span>.pc = disp; + } + TinyInsn::BranchZero(a, disp) => { + <span class="kw">if </span><span class="self">self</span>.read_reg(a) == <span class="number">0 </span>{ + <span class="self">self</span>.pc = disp; + } + } + } + } + } + + <span class="doccomment">/// Run in JIT mode until the next [`TinyInsn::Halt`] instruction is hit. Translate guest + /// _basic blocks_ on demand. + </span><span class="kw">pub fn </span>jit(<span class="kw-2">&mut </span><span class="self">self</span>) { + <span class="lifetime">'outer</span>: <span class="kw">loop </span>{ + <span class="kw">if let </span><span class="prelude-val">Some</span>(bb_fn) = <span class="self">self</span>.jit_cache[<span class="self">self</span>.pc] { + <span class="kw">match </span>bb_fn(<span class="self">self</span>.regs.as_mut_ptr(), <span class="self">self</span>.dmem.as_mut_ptr()) { + JitRet(<span class="number">0</span>, insn) => { + <span class="self">self</span>.pc += insn <span class="kw">as </span>usize; + <span class="self">self</span>.icnt += insn <span class="kw">as </span>usize; + <span class="kw">break </span><span class="lifetime">'outer</span>; + } + JitRet(insn, reenter_pc) => { + <span class="self">self</span>.pc = reenter_pc <span class="kw">as </span>usize; + <span class="self">self</span>.icnt += insn <span class="kw">as </span>usize; + } + } + } <span class="kw">else </span>{ + <span class="kw">let </span>bb_fn = <span class="self">self</span>.translate_next_bb(); + <span class="self">self</span>.jit_cache[<span class="self">self</span>.pc] = <span class="prelude-val">Some</span>(bb_fn); + <span class="comment">//println!("[0x{:02x}] translated bb at {:p}", self.pc, bb_fn); + </span>} + } + } + + <span class="doccomment">/// Translate the bb at the current pc and return a JitFn pointer to it. + </span><span class="kw">fn </span>translate_next_bb(<span class="kw-2">&mut </span><span class="self">self</span>) -> JitFn { + <span class="kw">let </span><span class="kw-2">mut </span>bb = Asm::new(); + <span class="kw">let </span><span class="kw-2">mut </span>pc = <span class="self">self</span>.pc; + + <span class="lifetime">'outer</span>: <span class="kw">loop </span>{ + <span class="kw">let </span>insn = <span class="self">self</span>.imem[pc]; + + pc = pc.wrapping_add(<span class="number">1</span>); + + <span class="comment">// JIT ABI. + // enter + // rdi => regs + // rsi => dmem + // exit + // rax => JitRet(0, + // rdx => 1) + + // Generate memory operand into regs for guest register. + </span><span class="kw">let </span>reg_op = |r: TinyReg| { + MemOp::IndirectDisp(Reg64::rdi, (r.idx() * <span class="number">2</span>).try_into().expect(<span class="string">"only 3 regs"</span>)) + }; + + <span class="comment">// Generate memory operand into dmem for guest phys address. + </span><span class="kw">let </span>mem_op = |paddr: u16| MemOp::IndirectDisp(Reg64::rsi, paddr.into()); + + <span class="comment">// Compute instructions in translated basic block. + </span><span class="kw">let </span>bb_icnt = || -> u64 { (pc - <span class="self">self</span>.pc).try_into().unwrap() }; + + <span class="kw">let </span>reenter_pc = |pc: usize| -> u64 { pc.try_into().unwrap() }; + + <span class="kw">match </span>insn { + TinyInsn::Halt => { + bb.mov(Reg64::rax, Imm64::from(<span class="number">0</span>)); + bb.mov(Reg64::rdx, Imm64::from(bb_icnt())); + bb.ret(); + <span class="kw">break </span><span class="lifetime">'outer</span>; + } + TinyInsn::LoadImm(a, imm) => { + bb.mov(reg_op(a), Imm16::from(imm)); + } + TinyInsn::Load(a, addr) => { + bb.mov(Reg16::ax, mem_op(addr)); + bb.mov(reg_op(a), Reg16::ax); + } + TinyInsn::Store(a, addr) => { + bb.mov(Reg16::ax, reg_op(a)); + bb.mov(mem_op(addr), Reg16::ax); + } + TinyInsn::Add(a, b) => { + bb.mov(Reg16::ax, reg_op(b)); + bb.add(reg_op(a), Reg16::ax); + } + TinyInsn::Addi(a, imm) => { + bb.add(reg_op(a), Imm16::from(imm)); + } + TinyInsn::Branch(disp) => { + bb.mov(Reg64::rax, Imm64::from(bb_icnt())); + bb.mov(Reg64::rdx, Imm64::from(reenter_pc(disp))); + bb.ret(); + <span class="kw">break </span><span class="lifetime">'outer</span>; + } + TinyInsn::BranchZero(a, disp) => { + bb.cmp(reg_op(a), Imm16::from(<span class="number">0u16</span>)); + bb.mov(Reg64::rax, Imm64::from(bb_icnt())); + bb.mov(Reg64::rdx, Imm64::from(reenter_pc(disp))); + + <span class="kw">let </span><span class="kw-2">mut </span>skip_next_pc = Label::new(); + <span class="comment">// If register is zero, skip setting next pc as reenter pc. + </span>bb.jz(<span class="kw-2">&mut </span>skip_next_pc); + bb.mov(Reg64::rdx, Imm64::from(reenter_pc(pc))); + bb.bind(<span class="kw-2">&mut </span>skip_next_pc); + bb.ret(); + <span class="kw">break </span><span class="lifetime">'outer</span>; + } + } + } + + <span class="kw">unsafe </span>{ <span class="self">self</span>.rt.add_code::<JitFn>(bb.into_code()) } + } +} + +<span class="doccomment">/// A minial fixup utility to implement jump labels when constructing guest programs. +</span><span class="kw">pub struct </span>Fixup { + pc: usize, +} + +<span class="kw">impl </span>Fixup { + <span class="doccomment">/// Create a new `Fixup` at the current pc. + </span><span class="kw">pub fn </span>new(pc: usize) -> <span class="self">Self </span>{ + Fixup { pc } + } + + <span class="doccomment">/// Bind the `Fixup` to the current location of `prog` and resolve the `Fixup`. + </span><span class="kw">pub fn </span>bind(<span class="self">self</span>, prog: <span class="kw-2">&mut </span>Vec<TinyInsn>) { + <span class="kw">let </span>plen = prog.len(); + <span class="kw">let </span>insn = prog.get_mut(<span class="self">self</span>.pc).expect(<span class="kw-2">&</span><span class="macro">format!</span>( + <span class="string">"Trying to apply Fixup, but Fixup is out of range pc={} prog.len={}"</span>, + <span class="self">self</span>.pc, plen + )); + + <span class="kw">match </span>insn { + TinyInsn::Branch(disp) | TinyInsn::BranchZero(<span class="kw">_</span>, disp) => { + <span class="kw-2">*</span>disp = plen; + } + <span class="kw">_ </span>=> { + <span class="macro">unimplemented!</span>(<span class="string">"Trying to fixup non-branch instruction '{:?}'"</span>, <span class="kw-2">*</span>insn); + } + } + } +} + +<span class="doccomment">/// Generate a guest program to compute the fiibonacci sequence for `n`. +</span><span class="kw">pub fn </span>make_tinyvm_fib(start_n: u16) -> Vec<TinyInsn> { + <span class="comment">// Reference implementation: + // + // int fib(int n) + // int tmp = 0; + // int prv = 1; + // int sum = 0; + // loop: + // if (n == 0) goto end; + // tmp = sum; + // sum += prv; + // prv = tmp; + // --n; + // goto loop; + // end: + // return sum; + + // Variables live in memory, bin to fixed addresses. + </span><span class="kw">let </span>tmp = <span class="number">0u16</span>; + <span class="kw">let </span>prv = <span class="number">2u16</span>; + <span class="kw">let </span>sum = <span class="number">4u16</span>; + <span class="comment">// Loop counter mapped to register. + </span><span class="kw">let </span>n = TinyReg::C; + + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::with_capacity(<span class="number">32</span>); + + <span class="comment">// n = start_n + </span>prog.push(TinyInsn::LoadImm(n, start_n)); + + <span class="comment">// tmp = sum = 0 + </span>prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">0</span>)); + prog.push(TinyInsn::Store(TinyReg::A, tmp)); + prog.push(TinyInsn::Store(TinyReg::A, sum)); + + <span class="comment">// prv = 1 + </span>prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">1</span>)); + prog.push(TinyInsn::Store(TinyReg::A, prv)); + + <span class="comment">// Create loop_start label. + </span><span class="kw">let </span>loop_start = prog.len(); + + <span class="comment">// Create fixup to capture PC that need to be patched later. + </span><span class="kw">let </span>end_fixup = Fixup::new(prog.len()); + + <span class="comment">// if (n == 0) goto end + </span>prog.push(TinyInsn::BranchZero(n, <span class="number">0xdead</span>)); + + <span class="comment">// tmp = sum + </span>prog.push(TinyInsn::Load(TinyReg::A, sum)); + prog.push(TinyInsn::Store(TinyReg::A, tmp)); + + <span class="comment">// sum += prv + </span>prog.push(TinyInsn::Load(TinyReg::B, prv)); + prog.push(TinyInsn::Add(TinyReg::A, TinyReg::B)); + prog.push(TinyInsn::Store(TinyReg::A, sum)); + + <span class="comment">// prv = tmp + </span>prog.push(TinyInsn::Load(TinyReg::A, tmp)); + prog.push(TinyInsn::Store(TinyReg::A, prv)); + + <span class="comment">// --n + </span>prog.push(TinyInsn::Addi(n, -<span class="number">1</span>)); + + <span class="comment">// goto loop_start + </span>prog.push(TinyInsn::Branch(loop_start)); + + <span class="comment">// Bind end fixup to current PC, to patch branch to jump to here. + </span>end_fixup.bind(<span class="kw-2">&mut </span>prog); + + <span class="comment">// TinyReg::A = sum + </span>prog.push(TinyInsn::Load(TinyReg::A, sum)); + + <span class="comment">// Halt the VM. + </span>prog.push(TinyInsn::Halt); + + prog +} + +<span class="doccomment">/// Generate a test program for the jit. +</span><span class="kw">pub fn </span>make_tinyvm_jit_test() -> Vec<TinyInsn> { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::with_capacity(<span class="number">32</span>); + + prog.push(TinyInsn::Branch(<span class="number">1</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">0x0010</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::B, <span class="number">0x0</span>)); + + <span class="kw">let </span>start = prog.len(); + <span class="kw">let </span>end = Fixup::new(prog.len()); + prog.push(TinyInsn::BranchZero(TinyReg::A, <span class="number">0xdead</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::C, <span class="number">0x1</span>)); + prog.push(TinyInsn::Add(TinyReg::B, TinyReg::C)); + prog.push(TinyInsn::Addi(TinyReg::A, -<span class="number">1</span>)); + prog.push(TinyInsn::Branch(start)); + end.bind(<span class="kw-2">&mut </span>prog); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">0xabcd</span>)); + prog.push(TinyInsn::Store(TinyReg::A, <span class="number">0xffff</span>)); + prog.push(TinyInsn::Load(TinyReg::C, <span class="number">0xffff</span>)); + prog.push(TinyInsn::Halt); + prog.push(TinyInsn::Halt); + prog.push(TinyInsn::Halt); + prog.push(TinyInsn::Halt); + + prog +} + +<span class="doccomment">/// Generate a simple count down loop to crunch some instructions. +</span><span class="kw">pub fn </span>make_tinyvm_jit_perf() -> Vec<TinyInsn> { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::with_capacity(<span class="number">32</span>); + + prog.push(TinyInsn::Halt); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">0xffff</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::B, <span class="number">1</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::C, <span class="number">2</span>)); + prog.push(TinyInsn::Addi(TinyReg::A, -<span class="number">1</span>)); + prog.push(TinyInsn::BranchZero(TinyReg::A, <span class="number">0</span>)); + prog.push(TinyInsn::Branch(<span class="number">2</span>)); + prog +} + +<span class="kw">fn </span>main() { + <span class="kw">let </span>use_jit = <span class="kw">match </span>std::env::args().nth(<span class="number">1</span>) { + <span class="prelude-val">Some</span>(a) <span class="kw">if </span>a == <span class="string">"-h" </span>|| a == <span class="string">"--help" </span>=> { + <span class="macro">println!</span>(<span class="string">"Usage: tiny_vm [mode]"</span>); + <span class="macro">println!</span>(<span class="string">""</span>); + <span class="macro">println!</span>(<span class="string">"Options:"</span>); + <span class="macro">println!</span>(<span class="string">" mode if mode is 'jit' then run in jit mode, else in interpreter mode"</span>); + std::process::exit(<span class="number">0</span>); + } + <span class="prelude-val">Some</span>(a) <span class="kw">if </span>a == <span class="string">"jit" </span>=> <span class="bool-val">true</span>, + <span class="kw">_ </span>=> <span class="bool-val">false</span>, + }; + + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(make_tinyvm_fib(<span class="number">42</span>)); + + <span class="kw">if </span>use_jit { + <span class="macro">println!</span>(<span class="string">"Run in jit mode.."</span>); + vm.jit(); + } <span class="kw">else </span>{ + <span class="macro">println!</span>(<span class="string">"Run in interpreter mode.."</span>); + vm.interp(); + } + vm.dump(); +} + +<span class="attr">#[cfg(test)] +</span><span class="kw">mod </span>test { + <span class="kw">use super</span>::<span class="kw-2">*</span>; + + <span class="kw">fn </span>fib_rs(n: u64) -> u64 { + <span class="kw">if </span>n < <span class="number">2 </span>{ + n + } <span class="kw">else </span>{ + <span class="kw">let </span><span class="kw-2">mut </span>fib_n_m1 = <span class="number">0</span>; + <span class="kw">let </span><span class="kw-2">mut </span>fib_n = <span class="number">1</span>; + <span class="kw">for _ in </span><span class="number">1</span>..n { + <span class="kw">let </span>tmp = fib_n + fib_n_m1; + fib_n_m1 = fib_n; + fib_n = tmp; + } + fib_n + } + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_fib_interp() { + <span class="kw">for </span>n <span class="kw">in </span><span class="number">0</span>..<span class="number">92 </span>{ + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(make_tinyvm_fib(n)); + vm.interp(); + + <span class="macro">assert_eq!</span>((fib_rs(n <span class="kw">as </span>u64) & <span class="number">0xffff</span>) <span class="kw">as </span>u16, vm.read_reg(TinyReg::A)); + } + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_fib_jit() { + <span class="kw">for </span>n <span class="kw">in </span><span class="number">0</span>..<span class="number">92 </span>{ + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(make_tinyvm_fib(n)); + vm.jit(); + + <span class="macro">assert_eq!</span>((fib_rs(n <span class="kw">as </span>u64) & <span class="number">0xffff</span>) <span class="kw">as </span>u16, vm.read_reg(TinyReg::A)); + } + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_fib_icnt() { + <span class="kw">let </span><span class="kw-2">mut </span>vm1 = TinyVm::new(make_tinyvm_fib(<span class="number">91</span>)); + vm1.interp(); + <span class="kw">let </span><span class="kw-2">mut </span>vm2 = TinyVm::new(make_tinyvm_fib(<span class="number">91</span>)); + vm2.jit(); + + <span class="macro">assert_eq!</span>(vm1.icnt, vm2.icnt); + <span class="macro">assert_eq!</span>(vm1.pc, vm2.pc); + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_jit_load_imm() { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::new(); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">0x1111</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::B, <span class="number">0x2222</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::C, <span class="number">0x3333</span>)); + prog.push(TinyInsn::Halt); + + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(prog); + vm.jit(); + + <span class="macro">assert_eq!</span>(<span class="number">0x1111</span>, vm.read_reg(TinyReg::A)); + <span class="macro">assert_eq!</span>(<span class="number">0x2222</span>, vm.read_reg(TinyReg::B)); + <span class="macro">assert_eq!</span>(<span class="number">0x3333</span>, vm.read_reg(TinyReg::C)); + + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.icnt); + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.pc); + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_jit_add() { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::new(); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">0</span>)); + prog.push(TinyInsn::Addi(TinyReg::A, <span class="number">123</span>)); + + prog.push(TinyInsn::LoadImm(TinyReg::B, <span class="number">100</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::C, <span class="number">200</span>)); + prog.push(TinyInsn::Add(TinyReg::B, TinyReg::C)); + prog.push(TinyInsn::Halt); + + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(prog); + vm.jit(); + + <span class="macro">assert_eq!</span>(<span class="number">123</span>, vm.read_reg(TinyReg::A)); + <span class="macro">assert_eq!</span>(<span class="number">300</span>, vm.read_reg(TinyReg::B)); + <span class="macro">assert_eq!</span>(<span class="number">200</span>, vm.read_reg(TinyReg::C)); + + <span class="macro">assert_eq!</span>(<span class="number">6</span>, vm.icnt); + <span class="macro">assert_eq!</span>(<span class="number">6</span>, vm.pc); + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_jit_load_store() { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::new(); + prog.push(TinyInsn::Load(TinyReg::A, <span class="number">0xffff</span>)); + + prog.push(TinyInsn::LoadImm(TinyReg::B, <span class="number">0xf00d</span>)); + prog.push(TinyInsn::Store(TinyReg::B, <span class="number">0x8000</span>)); + prog.push(TinyInsn::Halt); + + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(prog); + vm.write_mem(PhysAddr(<span class="number">0xffff</span>), <span class="number">0xaabb</span>); + vm.jit(); + + <span class="macro">assert_eq!</span>(<span class="number">0xaabb</span>, vm.read_reg(TinyReg::A)); + <span class="macro">assert_eq!</span>(<span class="number">0xf00d</span>, vm.read_mem(PhysAddr(<span class="number">0x8000</span>))); + + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.icnt); + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.pc); + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_jit_branch() { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::new(); + prog.push(TinyInsn::Branch(<span class="number">2</span>)); + prog.push(TinyInsn::Halt); + prog.push(TinyInsn::Branch(<span class="number">6</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">1</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::B, <span class="number">2</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::C, <span class="number">3</span>)); + prog.push(TinyInsn::Branch(<span class="number">1</span>)); + + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(prog); + vm.jit(); + + <span class="macro">assert_eq!</span>(<span class="number">0</span>, vm.read_reg(TinyReg::A)); + <span class="macro">assert_eq!</span>(<span class="number">0</span>, vm.read_reg(TinyReg::B)); + <span class="macro">assert_eq!</span>(<span class="number">0</span>, vm.read_reg(TinyReg::C)); + + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.icnt); + <span class="macro">assert_eq!</span>(<span class="number">2</span>, vm.pc); + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_jit_branch_zero() { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::new(); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">1</span>)); + prog.push(TinyInsn::BranchZero(TinyReg::A, <span class="number">5</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">0</span>)); + prog.push(TinyInsn::BranchZero(TinyReg::A, <span class="number">5</span>)); + prog.push(TinyInsn::LoadImm(TinyReg::B, <span class="number">22</span>)); + prog.push(TinyInsn::Halt); + + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(prog); + vm.jit(); + + <span class="macro">assert_eq!</span>(<span class="number">0</span>, vm.read_reg(TinyReg::A)); + <span class="macro">assert_eq!</span>(<span class="number">0</span>, vm.read_reg(TinyReg::B)); + <span class="macro">assert_eq!</span>(<span class="number">0</span>, vm.read_reg(TinyReg::C)); + + <span class="macro">assert_eq!</span>(<span class="number">5</span>, vm.icnt); + <span class="macro">assert_eq!</span>(<span class="number">6</span>, vm.pc); + } + + <span class="attr">#[test] + </span><span class="kw">fn </span>test_mixed() { + <span class="kw">let </span><span class="kw-2">mut </span>prog = Vec::new(); + prog.push(TinyInsn::LoadImm(TinyReg::A, <span class="number">100</span>)); + prog.push(TinyInsn::Add(TinyReg::B, TinyReg::A)); + prog.push(TinyInsn::Addi(TinyReg::C, <span class="number">100</span>)); + prog.push(TinyInsn::Halt); + + <span class="kw">let </span><span class="kw-2">mut </span>vm = TinyVm::new(prog); + vm.interp(); + + <span class="macro">assert_eq!</span>(<span class="number">100</span>, vm.read_reg(TinyReg::A)); + <span class="macro">assert_eq!</span>(<span class="number">100</span>, vm.read_reg(TinyReg::B)); + <span class="macro">assert_eq!</span>(<span class="number">100</span>, vm.read_reg(TinyReg::C)); + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.icnt); + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.pc); + + vm.pc = <span class="number">0</span>; + vm.jit(); + + <span class="macro">assert_eq!</span>(<span class="number">100</span>, vm.read_reg(TinyReg::A)); + <span class="macro">assert_eq!</span>(<span class="number">200</span>, vm.read_reg(TinyReg::B)); + <span class="macro">assert_eq!</span>(<span class="number">200</span>, vm.read_reg(TinyReg::C)); + <span class="macro">assert_eq!</span>(<span class="number">8</span>, vm.icnt); + <span class="macro">assert_eq!</span>(<span class="number">4</span>, vm.pc); + } +} +</code></pre></div></section></main></body></html>
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