Move instruction implementation in sub module and introduce insn prelude

4 files changed, 117 insertions, 108 deletions

diff --git a/src/insn.rs b/src/insn.rs
index bb1a380..7c74dd9 100644
--- a/src/insn.rs
+++ b/src/insn.rs
@@ -1,3 +1,7 @@
+mod prelude;
+
+mod mov;
+
 pub trait Mov<T, U> {
     fn mov(&mut self, op1: T, op2: U);
 }
diff --git a/src/insn/mov.rs b/src/insn/mov.rs
new file mode 100644
index 0000000..d930ade
--- /dev/null
+++ b/src/insn/mov.rs
@@ -0,0 +1,105 @@
+use super::prelude::*;
+
+// -- MOV : reg reg
+
+impl Mov<Reg64, Reg64> for Asm {
+    fn mov(&mut self, op1: Reg64, op2: Reg64) {
+        self.encode_rr(0x89, op1, op2);
+    }
+}
+
+impl Mov<Reg32, Reg32> for Asm {
+    fn mov(&mut self, op1: Reg32, op2: Reg32) {
+        self.encode_rr(0x89, op1, op2);
+    }
+}
+
+impl Mov<Reg16, Reg16> for Asm {
+    fn mov(&mut self, op1: Reg16, op2: Reg16) {
+        self.encode_rr(0x89, op1, op2);
+    }
+}
+
+impl Mov<Reg8, Reg8> for Asm {
+    fn mov(&mut self, op1: Reg8, op2: Reg8) {
+        self.encode_rr(0x88, op1, op2);
+    }
+}
+
+// -- MOV : mem reg
+
+impl Mov<MemOp, Reg64> for Asm {
+    fn mov(&mut self, op1: MemOp, op2: Reg64) {
+        self.encode_mr(0x89, op1, op2);
+    }
+}
+
+impl Mov<MemOp, Reg32> for Asm {
+    fn mov(&mut self, op1: MemOp, op2: Reg32) {
+        self.encode_mr(0x89, op1, op2);
+    }
+}
+
+impl Mov<MemOp, Reg16> for Asm {
+    fn mov(&mut self, op1: MemOp, op2: Reg16) {
+        self.encode_mr(0x89, op1, op2);
+    }
+}
+
+impl Mov<MemOp, Reg8> for Asm {
+    fn mov(&mut self, op1: MemOp, op2: Reg8) {
+        self.encode_mr(0x88, op1, op2);
+    }
+}
+
+// -- MOV : reg mem
+
+impl Mov<Reg64, MemOp> for Asm {
+    fn mov(&mut self, op1: Reg64, op2: MemOp) {
+        self.encode_rm(0x8b, op1, op2);
+    }
+}
+
+impl Mov<Reg32, MemOp> for Asm {
+    fn mov(&mut self, op1: Reg32, op2: MemOp) {
+        self.encode_rm(0x8b, op1, op2);
+    }
+}
+
+impl Mov<Reg16, MemOp> for Asm {
+    fn mov(&mut self, op1: Reg16, op2: MemOp) {
+        self.encode_rm(0x8b, op1, op2);
+    }
+}
+
+impl Mov<Reg8, MemOp> for Asm {
+    fn mov(&mut self, op1: Reg8, op2: MemOp) {
+        self.encode_rm(0x8a, op1, op2);
+    }
+}
+
+// -- MOV : reg imm
+
+impl Mov<Reg64, Imm64> for Asm {
+    fn mov(&mut self, op1: Reg64, op2: Imm64) {
+        self.encode_oi(0xb8, op1, op2);
+    }
+}
+
+impl Mov<Reg32, Imm32> for Asm {
+    fn mov(&mut self, op1: Reg32, op2: Imm32) {
+        self.encode_oi(0xb8, op1, op2);
+    }
+}
+
+impl Mov<Reg16, Imm16> for Asm {
+    fn mov(&mut self, op1: Reg16, op2: Imm16) {
+        self.encode_oi(0xb8, op1, op2);
+    }
+}
+
+impl Mov<Reg8, Imm8> for Asm {
+    fn mov(&mut self, op1: Reg8, op2: Imm8) {
+        self.encode_oi(0xb0, op1, op2);
+    }
+}
diff --git a/src/insn/prelude.rs b/src/insn/prelude.rs
new file mode 100644
index 0000000..703417a
--- /dev/null
+++ b/src/insn/prelude.rs
@@ -0,0 +1,6 @@
+pub use crate::Asm;
+pub use crate::MemOp;
+pub use crate::{Imm16, Imm32, Imm64, Imm8};
+pub use crate::{Reg16, Reg32, Reg64, Reg8};
+
+pub use crate::insn::Mov;
diff --git a/src/lib.rs b/src/lib.rs
index 23c9ca0..9eb2583 100644
--- a/src/lib.rs
+++ b/src/lib.rs
@@ -106,7 +106,7 @@ impl Asm {
 
         self.emit_optional(&[prefix, rex]);
         self.emit(&[opc]);
-        self.emit(&op2.bytes());
+        self.emit(op2.bytes());
     }
 
     fn encode_ri<T: Reg, U: Imm>(&mut self, opc: u8, opc_ext: u8, op1: T, op2: U)
@@ -127,7 +127,7 @@ impl Asm {
 
         self.emit_optional(&[prefix, rex]);
         self.emit(&[opc, modrm]);
-        self.emit(&op2.bytes());
+        self.emit(op2.bytes());
     }
 
     fn encode_mr<T: Reg>(&mut self, opc: u8, op1: MemOp, op2: T)
@@ -244,109 +244,3 @@ impl EncodeMR<Reg16> for Asm {
 }
 impl EncodeMR<Reg32> for Asm {}
 impl EncodeMR<Reg64> for Asm {}
-
-// -- Instruction implementations.
-
-// -- MOV : reg reg
-
-impl Mov<Reg64, Reg64> for Asm {
-    fn mov(&mut self, op1: Reg64, op2: Reg64) {
-        self.encode_rr(0x89, op1, op2);
-    }
-}
-
-impl Mov<Reg32, Reg32> for Asm {
-    fn mov(&mut self, op1: Reg32, op2: Reg32) {
-        self.encode_rr(0x89, op1, op2);
-    }
-}
-
-impl Mov<Reg16, Reg16> for Asm {
-    fn mov(&mut self, op1: Reg16, op2: Reg16) {
-        self.encode_rr(0x89, op1, op2);
-    }
-}
-
-impl Mov<Reg8, Reg8> for Asm {
-    fn mov(&mut self, op1: Reg8, op2: Reg8) {
-        self.encode_rr(0x88, op1, op2);
-    }
-}
-
-// -- MOV : mem reg
-
-impl Mov<MemOp, Reg64> for Asm {
-    fn mov(&mut self, op1: MemOp, op2: Reg64) {
-        self.encode_mr(0x89, op1, op2);
-    }
-}
-
-impl Mov<MemOp, Reg32> for Asm {
-    fn mov(&mut self, op1: MemOp, op2: Reg32) {
-        self.encode_mr(0x89, op1, op2);
-    }
-}
-
-impl Mov<MemOp, Reg16> for Asm {
-    fn mov(&mut self, op1: MemOp, op2: Reg16) {
-        self.encode_mr(0x89, op1, op2);
-    }
-}
-
-impl Mov<MemOp, Reg8> for Asm {
-    fn mov(&mut self, op1: MemOp, op2: Reg8) {
-        self.encode_mr(0x88, op1, op2);
-    }
-}
-
-// -- MOV : reg mem
-
-impl Mov<Reg64, MemOp> for Asm {
-    fn mov(&mut self, op1: Reg64, op2: MemOp) {
-        self.encode_rm(0x8b, op1, op2);
-    }
-}
-
-impl Mov<Reg32, MemOp> for Asm {
-    fn mov(&mut self, op1: Reg32, op2: MemOp) {
-        self.encode_rm(0x8b, op1, op2);
-    }
-}
-
-impl Mov<Reg16, MemOp> for Asm {
-    fn mov(&mut self, op1: Reg16, op2: MemOp) {
-        self.encode_rm(0x8b, op1, op2);
-    }
-}
-
-impl Mov<Reg8, MemOp> for Asm {
-    fn mov(&mut self, op1: Reg8, op2: MemOp) {
-        self.encode_rm(0x8a, op1, op2);
-    }
-}
-
-// -- MOV : reg imm
-
-impl Mov<Reg64, Imm64> for Asm {
-    fn mov(&mut self, op1: Reg64, op2: Imm64) {
-        self.encode_oi(0xb8, op1, op2);
-    }
-}
-
-impl Mov<Reg32, Imm32> for Asm {
-    fn mov(&mut self, op1: Reg32, op2: Imm32) {
-        self.encode_oi(0xb8, op1, op2);
-    }
-}
-
-impl Mov<Reg16, Imm16> for Asm {
-    fn mov(&mut self, op1: Reg16, op2: Imm16) {
-        self.encode_oi(0xb8, op1, op2);
-    }
-}
-
-impl Mov<Reg8, Imm8> for Asm {
-    fn mov(&mut self, op1: Reg8, op2: Imm8) {
-        self.encode_oi(0xb0, op1, op2);
-    }
-}