clippy: fix some clippy lints

2 files changed, 30 insertions, 50 deletions

diff --git a/src/imm.rs b/src/imm.rs
index 85b2cbc..ee51ae5 100644
--- a/src/imm.rs
+++ b/src/imm.rs
@@ -46,5 +46,18 @@ impl_imm!(
 );
 impl_imm!(
     /// Type representing a 64 bit immediate.
-    Imm64, 8, from: { u64, i64, u32, i32, u16, i16, u8, i8 }
+    Imm64, 8, from: { u64, i64, u32, i32, u16, i16, u8, i8, usize, isize }
 );
+
+#[cfg(test)]
+mod test {
+    use super::*;
+    use std::mem::size_of;
+
+    #[test]
+    fn test_usize_isize() {
+        // Imm64 should not implementd from usize/isize if this fails.
+        assert_eq!(size_of::<usize>(), size_of::<Imm64>());
+        assert_eq!(size_of::<isize>(), size_of::<Imm64>());
+    }
+}
\ No newline at end of file
diff --git a/src/reg.rs b/src/reg.rs
index 2dc2281..15417c4 100644
--- a/src/reg.rs
+++ b/src/reg.rs
@@ -155,27 +155,18 @@ mod tests {
             assert_eq!(r.idx(), idx);
 
             // Check REX.W bit.
-            assert_eq!(r.rexw(), false);
+            assert!(!r.rexw());
 
             // Check need REX byte.
-            let rex = match r {
-                r8l | r9l | r10l | r11l | r12l | r13l | r14l | r15l | spl | bpl | sil | dil => true,
-                _ => false,
-            };
+            let rex = matches!(r, r8l | r9l | r10l | r11l | r12l | r13l | r14l | r15l | spl | bpl | sil | dil);
             assert_eq!(r.need_rex(), rex);
 
             // Check need SIB byte.
-            let sib = match r {
-                spl | r12l | ah => true,
-                _ => false,
-            };
+            let sib = matches!(r, spl | r12l | ah);
             assert_eq!(r.need_sib(), sib);
 
             // Check if is PC relative addressing.
-            let rel = match r {
-                bpl | r13l | ch => true,
-                _ => false,
-            };
+            let rel = matches!(r, bpl | r13l | ch);
             assert_eq!(r.is_pc_rel(), rel);
         }
     }
@@ -207,27 +198,18 @@ mod tests {
             assert_eq!(r.idx(), idx);
 
             // Check REX.W bit.
-            assert_eq!(r.rexw(), false);
+            assert!(!r.rexw());
 
             // Check need REX byte.
-            let rex = match r {
-                r8w | r9w | r10w | r11w | r12w | r13w | r14w | r15w => true,
-                _ => false,
-            };
+            let rex = matches!(r, r8w | r9w | r10w | r11w | r12w | r13w | r14w | r15w);
             assert_eq!(r.need_rex(), rex);
 
             // Check need SIB byte.
-            let sib = match r {
-                sp | r12w => true,
-                _ => false,
-            };
+            let sib = matches!(r, sp | r12w);
             assert_eq!(r.need_sib(), sib);
 
             // Check if is PC relative addressing.
-            let rel = match r {
-                bp | r13w => true,
-                _ => false,
-            };
+            let rel = matches!(r, bp | r13w);
             assert_eq!(r.is_pc_rel(), rel);
         }
     }
@@ -259,27 +241,18 @@ mod tests {
             assert_eq!(r.idx(), idx);
 
             // Check REX.W bit.
-            assert_eq!(r.rexw(), false);
+            assert!(!r.rexw());
 
             // Check need REX byte.
-            let rex = match r {
-                r8d | r9d | r10d | r11d | r12d | r13d | r14d | r15d => true,
-                _ => false,
-            };
+            let rex = matches!(r, r8d | r9d | r10d | r11d | r12d | r13d | r14d | r15d);
             assert_eq!(r.need_rex(), rex);
 
             // Check need SIB byte.
-            let sib = match r {
-                esp | r12d => true,
-                _ => false,
-            };
+            let sib = matches!(r, esp | r12d);
             assert_eq!(r.need_sib(), sib);
 
             // Check if is PC relative addressing.
-            let rel = match r {
-                ebp | r13d => true,
-                _ => false,
-            };
+            let rel = matches!(r, ebp | r13d);
             assert_eq!(r.is_pc_rel(), rel);
         }
     }
@@ -311,23 +284,17 @@ mod tests {
             assert_eq!(r.idx(), idx);
 
             // Check REX.W bit.
-            assert_eq!(r.rexw(), true);
+            assert!(r.rexw());
 
             // Check need REX byte.
-            assert_eq!(r.need_rex(), true);
+            assert!(r.need_rex());
 
             // Check need SIB byte.
-            let sib = match r {
-                rsp | r12 => true,
-                _ => false,
-            };
+            let sib = matches!(r, rsp | r12);
             assert_eq!(r.need_sib(), sib);
 
             // Check if is PC relative addressing.
-            let rel = match r {
-                rbp | r13 => true,
-                _ => false,
-            };
+            let rel = matches!(r, rbp | r13);
             assert_eq!(r.is_pc_rel(), rel);
         }
     }