3 files changed, 32 insertions, 5 deletions
diff --git a/src/insn.rs b/src/insn.rs
index 8c2215c..90ce444 100644
--- a/src/insn.rs
+++ b/src/insn.rs
@@ -15,6 +15,7 @@ mod nop;
 mod pop;
 mod push;
 mod ret;
+mod sub;
 mod test;
 mod xor;
 
@@ -91,16 +92,22 @@ pub trait Mov<T, U> {
     fn mov(&mut self, op1: T, op2: U);
 }
 
+/// Trait for [`pop`](https://www.felixcloutier.com/x86/pop) instruction kinds.
+pub trait Pop<T> {
+    /// Emit a pop instruction.
+    fn pop(&mut self, op1: T);
+}
+
 /// Trait for [`push`](https://www.felixcloutier.com/x86/push) instruction kinds.
 pub trait Push<T> {
     /// Emit a push instruction.
     fn push(&mut self, op1: T);
 }
 
-/// Trait for [`pop`](https://www.felixcloutier.com/x86/pop) instruction kinds.
-pub trait Pop<T> {
-    /// Emit a pop instruction.
-    fn pop(&mut self, op1: T);
+/// Trait for [`sub`](https://www.felixcloutier.com/x86/sub) instruction kinds.
+pub trait Sub<T, U> {
+    /// Emit an sub instruction.
+    fn sub(&mut self, op1: T, op2: U);
 }
 
 /// Trait for [`test`](https://www.felixcloutier.com/x86/test) instruction kinds.
diff --git a/src/insn/add.rs b/src/insn/add.rs
index d5312be..1f5294e 100644
--- a/src/insn/add.rs
+++ b/src/insn/add.rs
@@ -1,5 +1,5 @@
 use super::Add;
-use crate::{Asm, Imm16, MemOp, Reg16, Reg32, Reg64};
+use crate::{Asm, Imm16, Imm8, MemOp, Reg16, Reg32, Reg64};
 
 impl Add<Reg64, Reg64> for Asm {
     fn add(&mut self, op1: Reg64, op2: Reg64) {
@@ -25,6 +25,12 @@ impl Add<MemOp, Reg16> for Asm {
     }
 }
 
+impl Add<MemOp, Imm8> for Asm {
+    fn add(&mut self, op1: MemOp, op2: Imm8) {
+        self.encode_mi(0x83, 0, op1, op2);
+    }
+}
+
 impl Add<MemOp, Imm16> for Asm {
     fn add(&mut self, op1: MemOp, op2: Imm16) {
         self.encode_mi(0x81, 0, op1, op2);
diff --git a/src/insn/sub.rs b/src/insn/sub.rs
new file mode 100644
index 0000000..814744c
--- /dev/null
+++ b/src/insn/sub.rs
@@ -0,0 +1,14 @@
+use super::Sub;
+use crate::{Asm, Imm8, MemOp, Reg64};
+
+impl Sub<Reg64, Reg64> for Asm {
+    fn sub(&mut self, op1: Reg64, op2: Reg64) {
+        self.encode_rr(&[0x29], op1, op2);
+    }
+}
+
+impl Sub<MemOp, Imm8> for Asm {
+    fn sub(&mut self, op1: MemOp, op2: Imm8) {
+        self.encode_mi(0x83, 5, op1, op2);
+    }
+}