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-rw-r--r--lib/arch/riscv64/README.md1
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@@ -8,5 +8,6 @@ Provide an implementation of the platform specific API as required in
- Callee saved registers `x2`, `x8` - `x9`, `x18` - `x27`, `f8` - `f9`, `f18` - `f27`
## References
+- [johannst riscv notes](https://johannst.github.io/notes/arch/riscv.html)
- [RISC-V ABI](https://github.com/riscv/riscv-elf-psabi-doc/blob/master/riscv-elf.md)
- [RISC-V asm manual](https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md)