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</pre></div><pre class="rust"><code><span class="doccomment">//! `x86_64` flags and bitfields.
</span><span class="kw">pub use </span>x86_64::<span class="kw-2">*</span>;
<span class="attr">#[rustfmt::skip]
</span><span class="kw">mod </span>x86_64 {
<span class="comment">/* Rflags Register */
</span><span class="doccomment">/// Carry flag.
</span><span class="kw">pub const </span>RFLAGS_CF: u64 = <span class="number">1 </span><< <span class="number">0</span>;
<span class="doccomment">/// Parity flag.
</span><span class="kw">pub const </span>RFLAGS_PF: u64 = <span class="number">1 </span><< <span class="number">2</span>;
<span class="doccomment">/// Adjust flag.
</span><span class="kw">pub const </span>RFLAGS_AF: u64 = <span class="number">1 </span><< <span class="number">4</span>;
<span class="doccomment">/// Zero flag.
</span><span class="kw">pub const </span>RFLAGS_ZF: u64 = <span class="number">1 </span><< <span class="number">6</span>;
<span class="doccomment">/// Sign flag.
</span><span class="kw">pub const </span>RFLAGS_SF: u64 = <span class="number">1 </span><< <span class="number">7</span>;
<span class="doccomment">/// Trap flag.
</span><span class="kw">pub const </span>RFLAGS_TF: u64 = <span class="number">1 </span><< <span class="number">8</span>;
<span class="doccomment">/// Sign flag.
</span><span class="kw">pub const </span>RFLAGS_IF: u64 = <span class="number">1 </span><< <span class="number">9</span>;
<span class="doccomment">/// Direction flag.
</span><span class="kw">pub const </span>RFLAGS_DF: u64 = <span class="number">1 </span><< <span class="number">10</span>;
<span class="doccomment">/// Overflow flag.
</span><span class="kw">pub const </span>RFLAGS_OF: u64 = <span class="number">1 </span><< <span class="number">11</span>;
<span class="doccomment">/// I/O privilege level.
</span><span class="kw">pub const </span>RFLAGS_IOPL: u64 = <span class="number">0b11 </span><< <span class="number">12</span>;
<span class="doccomment">/// Alignment check.
</span><span class="kw">pub const </span>RFLAGS_AC: u64 = <span class="number">1 </span><< <span class="number">18</span>;
<span class="kw">pub const fn </span>rflags_cf(r: u64) -> u64 { (r & RFLAGS_CF) >> <span class="number">0 </span>}
<span class="kw">pub const fn </span>rflags_pf(r: u64) -> u64 { (r & RFLAGS_PF) >> <span class="number">2 </span>}
<span class="kw">pub const fn </span>rflags_af(r: u64) -> u64 { (r & RFLAGS_AF) >> <span class="number">4 </span>}
<span class="kw">pub const fn </span>rflags_zf(r: u64) -> u64 { (r & RFLAGS_ZF) >> <span class="number">6 </span>}
<span class="kw">pub const fn </span>rflags_sf(r: u64) -> u64 { (r & RFLAGS_SF) >> <span class="number">7 </span>}
<span class="kw">pub const fn </span>rflags_tf(r: u64) -> u64 { (r & RFLAGS_TF) >> <span class="number">8 </span>}
<span class="kw">pub const fn </span>rflags_if(r: u64) -> u64 { (r & RFLAGS_IF) >> <span class="number">9 </span>}
<span class="kw">pub const fn </span>rflags_df(r: u64) -> u64 { (r & RFLAGS_DF) >> <span class="number">10 </span>}
<span class="kw">pub const fn </span>rflags_of(r: u64) -> u64 { (r & RFLAGS_OF) >> <span class="number">11 </span>}
<span class="kw">pub const fn </span>rflags_iopl(r: u64) -> u64 { (r & RFLAGS_IOPL) >> <span class="number">12 </span>}
<span class="kw">pub const fn </span>rflags_ac(r: u64) -> u64 { (r & RFLAGS_AC) >> <span class="number">18 </span>}
<span class="comment">/* Segment Selector */
</span><span class="doccomment">/// Requested privilege level.
///
/// Privilege level of the segment selector, where `0` is the most privileged mode and `3` the
/// least.
</span><span class="kw">pub const </span>SEG_SELECTOR_RPL: u16 = <span class="number">0b11 </span><< <span class="number">0</span>;
<span class="doccomment">/// Table indicator.
///
/// | TI | Table |
/// |----|-------|
/// | 0 | GDT |
/// | 1 | LDT |
</span><span class="kw">pub const </span>SEG_SELECTOR_TI: u16 = <span class="number">1 </span><< <span class="number">2</span>;
<span class="doccomment">/// Table index.
///
/// Index into the `GDT` or `LDT` table to select the segment descriptor. `GDT.base + 8 * index`
/// gives the address of the segment descriptor (times `8` because every segment descriptor is `8
/// byte`).
</span><span class="kw">pub const </span>SEG_SELECTOR_INDEX: u16 = <span class="number">0x1fff </span><< <span class="number">3</span>;
<span class="kw">pub const fn </span>seg_selector_rpl(s: u16) -> u16 { (s & SEG_SELECTOR_RPL) >> <span class="number">0 </span>}
<span class="kw">pub const fn </span>seg_selector_ti(s: u16) -> u16 { (s & SEG_SELECTOR_TI) >> <span class="number">2 </span>}
<span class="kw">pub const fn </span>seg_selector_index(s: u16) -> u16 { (s & SEG_SELECTOR_INDEX) >> <span class="number">3 </span>}
<span class="comment">/* Control Register CR0 (operation mode & state of the processor) */
</span><span class="doccomment">/// Protection Enable.
///
/// Enables `protected mode` when set and `real-address mode` when cleared. This enables
/// `segment-level protection` not paging.
</span><span class="kw">pub const </span>CR0_PE: u64 = <span class="number">1 </span><< <span class="number">0</span>;
<span class="doccomment">/// Monitor Coprocessor.
</span><span class="kw">pub const </span>CR0_MP: u64 = <span class="number">1 </span><< <span class="number">1</span>;
<span class="doccomment">/// Emulation.
///
/// When set indicates the process does not have a FPU. FPU instructions will generate an exception
/// that software can emulate the instruction.
</span><span class="kw">pub const </span>CR0_EM: u64 = <span class="number">1 </span><< <span class="number">2</span>;
<span class="doccomment">/// Task Switched.
</span><span class="kw">pub const </span>CR0_TS: u64 = <span class="number">1 </span><< <span class="number">3</span>;
<span class="doccomment">/// Extension Type.
</span><span class="kw">pub const </span>CR0_ET: u64 = <span class="number">1 </span><< <span class="number">4</span>;
<span class="doccomment">/// Numeric Error.
</span><span class="kw">pub const </span>CR0_NE: u64 = <span class="number">1 </span><< <span class="number">5</span>;
<span class="doccomment">/// Write Protect.
///
/// When set supervisor-level procedures can't write to read-only pages.
</span><span class="kw">pub const </span>CR0_WP: u64 = <span class="number">1 </span><< <span class="number">16</span>;
<span class="doccomment">/// Alignment Mask.
///
/// Enables alignment check for `CPL=3`, check is only done if the [AC
/// bit](crate::x86_64::RFLAGS_AC) of the `rflags` register ist set.
</span><span class="kw">pub const </span>CR0_AM: u64 = <span class="number">1 </span><< <span class="number">18</span>;
<span class="doccomment">/// Not Write-Torugh.
</span><span class="kw">pub const </span>CR0_NW: u64 = <span class="number">1 </span><< <span class="number">29</span>;
<span class="doccomment">/// Cachine disable.
</span><span class="kw">pub const </span>CR0_CD: u64 = <span class="number">1 </span><< <span class="number">30</span>;
<span class="doccomment">/// Paging.
///
/// Enables paging when set, requires [CR0_PE](crate::x86_64::CR0_PE) to be set as well.
</span><span class="kw">pub const </span>CR0_PG: u64 = <span class="number">1 </span><< <span class="number">31</span>;
<span class="comment">/* Control Register CR3 (paging information)
*
* Holds the physical base address of the first paging structure. The 12 lower bytes of the base
* address are assumed to be 0 and hence the first paging structure must be aligned to a 4K
* boundary.
*/
</span><span class="doccomment">/// Mask for physical base address of paging structure.
</span><span class="kw">pub const </span>CR3_PAGE_BASE_MASK: u64 = <span class="number">0xffff_ffff_ffff_0000</span>;
<span class="doccomment">/// Page-level Write-Through.
</span><span class="kw">pub const </span>CR3_PWT: u64 = <span class="number">1 </span><< <span class="number">3</span>;
<span class="doccomment">/// Page-level Cache Disable.
</span><span class="kw">pub const </span>CR3_PCD: u64 = <span class="number">1 </span><< <span class="number">4</span>;
<span class="comment">/* Control Register CR4 (flags for arch extenstions processor capabilities) */
</span><span class="doccomment">/// Physical Address Extenstion.
///
/// When set enables paging to produce physicall addresses with more than 32 bits. Required before
/// entering `long mode`.
</span><span class="kw">pub const </span>CR4_PAE: u64 = <span class="number">1 </span><< <span class="number">5</span>;
<span class="doccomment">/// 57-bit Linear Addresses.
///
/// When set in `long mode` enables `5-level` paging to translate `57-bit` linear addresses. When
/// cleared use `4-level` paging to translate `48-bit` linear addresses.
</span><span class="kw">pub const </span>CR4_LA57: u64 = <span class="number">1 </span><< <span class="number">5</span>;
<span class="comment">/* Extended Feature Enable Register (EFER) */
</span><span class="doccomment">/// Extended Feature Enable Register MSR number.
///
/// MSR number used with the [`rdmsr`][msr] and [`wrmsr`][msr] instructions to read/write the
/// `EFER` model specific register.
///
/// [msr]: https://johannst.github.io/notes/arch/x86_64.html#model-specific-register-msr
</span><span class="kw">pub const </span>MSR_EFER: u64 = <span class="number">0xc000_0080</span>;
<span class="doccomment">/// Long Mode Enable.
///
/// When set enables long mode operations.
</span><span class="kw">pub const </span>EFER_LME: u64 = <span class="number">1 </span><< <span class="number">8</span>;
<span class="doccomment">/// Long Mode Active (readonly).
///
/// When set indicates long mode is active.
</span><span class="kw">pub const </span>EFER_LMA: u64 = <span class="number">1 </span><< <span class="number">10</span>;
<span class="comment">/* Paging */
</span><span class="doccomment">/// Page entry present.
</span><span class="kw">pub const </span>PAGE_ENTRY_PRESENT: u64 = <span class="number">1 </span><< <span class="number">0</span>;
<span class="doccomment">/// Page region read/write.
///
/// If set, region reference by paging entry is writeable.
</span><span class="kw">pub const </span>PAGE_ENTRY_RW: u64 = <span class="number">1 </span><< <span class="number">1</span>;
}
</code></pre></div></section></main></body></html>
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