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authorJohannes Stoelp <johannes.stoelp@gmail.com>2021-11-27 23:43:51 +0100
committerJohannes Stoelp <johannes.stoelp@gmail.com>2021-11-27 23:43:51 +0100
commita21db4db6af4987ad4ec81e1fb6d6ee4f9fc2695 (patch)
treeb9a48cdaae30204a3d9ed9a3df8cacd6df6f6a2b /src/arch
parentcad6375d3e36538ab44a5bdd1fbbf5acd420fc1b (diff)
downloadnotes-a21db4db6af4987ad4ec81e1fb6d6ee4f9fc2695.tar.gz
notes-a21db4db6af4987ad4ec81e1fb6d6ee4f9fc2695.zip
armv7: update notes on addressing
Diffstat (limited to 'src/arch')
-rw-r--r--src/arch/armv7.md11
1 files changed, 7 insertions, 4 deletions
diff --git a/src/arch/armv7.md b/src/arch/armv7.md
index f6c3a96..2618938 100644
--- a/src/arch/armv7.md
+++ b/src/arch/armv7.md
@@ -71,10 +71,13 @@ blx <Rm> // absolute branch to address in register Rm &
### Load/Store
Different addressing modes.
```armasm
-str r1, [r0] // [r0]=r1
-str r1, [r0, #4] // [r0+4]=r1
-str r1, [r0, #4]! // r0+=4; [r0]=r1
-str r1, [r0], 4 // [r0]=r1; r0+=4
+ldr r1, [r0] // r1 = [r0]
+ldr r1, [r0, #4] // r1 = [r0+4]
+
+ldr r1, [r0, #4]! // pre-inc : r0+=4; r1 = [r0]
+ldr r1, [r0], #4 // post-inc: [r0] = r1; r0+=4
+
+ldr r0, [r1, r2, lsl #3] // r0 = [r1 + (r2<<3)]
```
Load/store multiple registers full-descending.