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| author | Johannes Stoelp <johannes.stoelp@gmail.com> | 2024-05-01 19:25:37 +0200 |
|---|---|---|
| committer | Johannes Stoelp <johannes.stoelp@gmail.com> | 2024-05-01 19:25:37 +0200 |
| commit | 39b4e0bf8a3b02f1606a0efeefeb39891242bf99 (patch) | |
| tree | 6c7b86750524ade4747b09092ef7048ec70d8fe4 /src | |
| parent | 10d1d2a6124935e5ec9d76e50f67df8f582e112f (diff) | |
| download | notes-39b4e0bf8a3b02f1606a0efeefeb39891242bf99.tar.gz notes-39b4e0bf8a3b02f1606a0efeefeb39891242bf99.zip | |
armv8: add overview notes
Diffstat (limited to 'src')
| -rw-r--r-- | src/SUMMARY.md | 1 | ||||
| -rw-r--r-- | src/arch/README.md | 1 | ||||
| -rw-r--r-- | src/arch/arm64.md | 4 | ||||
| -rw-r--r-- | src/arch/armv8.md | 47 |
4 files changed, 53 insertions, 0 deletions
diff --git a/src/SUMMARY.md b/src/SUMMARY.md index 24c679f..8a095a5 100644 --- a/src/SUMMARY.md +++ b/src/SUMMARY.md @@ -90,6 +90,7 @@ - [Arch](./arch/README.md) - [x86_64](./arch/x86_64.md) + - [armv8](./arch/armv8.md) - [arm64](./arch/arm64.md) - [armv7](./arch/armv7.md) - [riscv](./arch/riscv.md) diff --git a/src/arch/README.md b/src/arch/README.md index a3dc3d5..a0185e3 100644 --- a/src/arch/README.md +++ b/src/arch/README.md @@ -1,6 +1,7 @@ # Arch - [x86_64](./x86_64.md) +- [armv8](./armv8.md) - [arm64](./arm64.md) - [armv7](./armv7.md) - [riscv](./riscv.md) diff --git a/src/arch/arm64.md b/src/arch/arm64.md index ada6bf5..d999e5a 100644 --- a/src/arch/arm64.md +++ b/src/arch/arm64.md @@ -1,4 +1,8 @@ # arm64 + +> This page only talks about the 64 bit part of the `armv8` architecture. For +> an overview see [`armv8`](./armv8.md). + keywords: arm64, aarch64, abi - 64bit synonyms: `arm64`, `aarch64` diff --git a/src/arch/armv8.md b/src/arch/armv8.md new file mode 100644 index 0000000..17290cc --- /dev/null +++ b/src/arch/armv8.md @@ -0,0 +1,47 @@ +# armv8 + +keywords: aarch64, arm64, A64, aarch32, A32, T32, abi + +The `armv8` architecture introduces support for 64-bit and defines two +*execution states* `aarch64` and `aarch32`. + +Implementations are **not** required to implement all execution states for all +*exception levels (EL)*. For example the [coretex-a32][coretex-a32] only +implements `aarch32`, while the [coretex-a34][coretex-a34] only implements +`aarch64`. + +The execution states support different instruction sets. +- `aarch64` only supports the new [`A64`][a64] instruction set, where all + instructions have the fixed size of of 32 bits. +- `aarch32` supports the [`A32`][a32] and [`T32`][t32] instruction sets. These + are updated versions of the `armv7` instruction sets, kept backwards + compatible allowing `armv7` programs to run on `armv8`. + > In `armv7` the instruction sets `A32` an `T32` were called `arm` and + > `thumb` respectively. + +A *program* always runs in either the `aarch64` or the `aarch32` execution +state, but never in a *mixture* of both. Transitions between execution states +only occur when raising or lowering the exception level. +- `aarch64 -> aarch32` can only occur when switching from *higher EL* to *lower + EL*. +- `aarch32 -> aarch64` can only occur when switching from *lower EL* to *higher + EL*. + +The following figure depicts which execution state Transitions are allowed. +``` + (user) EL0 ^ | + (os) EL1 | 32->64 +(hypervisor) EL2 64->32 | + (secure) EL3 | v +``` +This means for example, an *os* running in `aarch32` can only support `aarch32` +user applications, while an *os* running in `aarch64` can support +`aarch32 / aarch64` user applications. + + +[coretex-a32]: https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a32 +[coretex-a34]: https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a34 + +[a32]: https://developer.arm.com/documentation/ddi0597/latest +[t32]: https://developer.arm.com/documentation/ddi0597/latest +[a64]: https://developer.arm.com/documentation/ddi0602/latest |