lt_bus: minor renamings

1 files changed, 32 insertions, 32 deletions

diff --git a/src/models/lt_bus.h b/src/models/lt_bus.h
index 9b16ab9..cf09d99 100644
--- a/src/models/lt_bus.h
+++ b/src/models/lt_bus.h
@@ -51,13 +51,13 @@ class lt_bus : public sc_core::sc_module {
     const range addr{start, end};
 
     // Check if new range overlaps with any registered memory map range.
-    for (const auto& map : m_mappings) {
-      if (map.addr.overlaps(addr)) {
+    for (const auto& mmap : m_mappings) {
+      if (mmap.addr.overlaps(addr)) {
         std::fprintf(stderr,
                      "lt_bus: memory map conflict detected\n"
                      "old: %08lx - %08lx\n"
                      "new: %08lx - %08lx\n",
-                     map.addr.start, map.addr.end, start, end);
+                     mmap.addr.start, mmap.addr.end, start, end);
         std::abort();
       }
     }
@@ -85,9 +85,9 @@ class lt_bus : public sc_core::sc_module {
 
   void show_mmap() const {
     // Dump memory map.
-    for (const auto& map : m_mappings) {
-      std::printf("%08lx - %08lx :[%2ld] %s\n", map.addr.start, map.addr.end,
-                  map.idx, m_targets[map.idx].get()->name());
+    for (const auto& mmap : m_mappings) {
+      std::printf("%08lx - %08lx :[%2ld] %s\n", mmap.addr.start, mmap.addr.end,
+                  mmap.idx, m_targets[mmap.idx].get()->name());
     }
   }
 
@@ -99,14 +99,14 @@ class lt_bus : public sc_core::sc_module {
                                  sc_dt::uint64 end) {
     assert(start <= end);
 
-    for (const auto& map : m_mappings) {
-      if (map.idx != id) {
+    for (const auto& mmap : m_mappings) {
+      if (mmap.idx != id) {
         continue;
       }
 
       // Compute absolute start/end address based on memory map.
       const range abs_addr =
-          compute_abs_mmap_address(range{start, end}, map.addr);
+          compute_abs_mmap_address(range{start, end}, mmap.addr);
 
       for (auto& sock : m_initiators) {
         (*sock)->invalidate_direct_mem_ptr(abs_addr.start, abs_addr.end);
@@ -118,12 +118,12 @@ class lt_bus : public sc_core::sc_module {
 
   void b_transport(usize, tlm::tlm_generic_payload& tx, sc_core::sc_time& t) {
     if (const auto r = decode(tx)) {
-      const auto start = tx.get_address();
-      assert(r.start <= start);
+      const auto tx_start = tx.get_address();
+      assert(r.start <= tx_start);
 
-      tx.set_address(start - r.start);
+      tx.set_address(tx_start - r.start);
       (*r.sock)->b_transport(tx, t);
-      tx.set_address(start);
+      tx.set_address(tx_start);
     } else {
       tx.set_response_status(tlm::TLM_ADDRESS_ERROR_RESPONSE);
     }
@@ -133,12 +133,12 @@ class lt_bus : public sc_core::sc_module {
                           tlm::tlm_generic_payload& tx,
                           tlm::tlm_dmi& dmi) {
     if (const auto r = decode(tx)) {
-      const auto start = tx.get_address();
-      assert(r.start <= start);
+      const auto tx_start = tx.get_address();
+      assert(r.start <= tx_start);
 
-      tx.set_address(start - r.start);
+      tx.set_address(tx_start - r.start);
       const bool ok = (*r.sock)->get_direct_mem_ptr(tx, dmi);
-      tx.set_address(start);
+      tx.set_address(tx_start);
 
       // Early return, dmi request failed, no need to fixup dmi addresses.
       if (!ok) {
@@ -162,12 +162,12 @@ class lt_bus : public sc_core::sc_module {
   unsigned int transport_dbg(usize, tlm::tlm_generic_payload& tx) {
     unsigned int ret = 0;
     if (const auto r = decode(tx)) {
-      const auto start = tx.get_address();
-      assert(r.start <= start);
+      const auto tx_start = tx.get_address();
+      assert(r.start <= tx_start);
 
-      tx.set_address(start - r.start);
+      tx.set_address(tx_start - r.start);
       ret = (*r.sock)->transport_dbg(tx);
-      tx.set_address(start);
+      tx.set_address(tx_start);
     }
     return ret;
   }
@@ -185,9 +185,9 @@ class lt_bus : public sc_core::sc_module {
   };
 
   decode_result decode(range addr) const {
-    for (const auto& map : m_mappings) {
-      if (map.addr.contains(addr)) {
-        return {m_targets[map.idx].get(), map.addr.start, map.addr.end};
+    for (const auto& mmap : m_mappings) {
+      if (mmap.addr.contains(addr)) {
+        return {m_targets[mmap.idx].get(), mmap.addr.start, mmap.addr.end};
       }
     }
     return {};
@@ -201,21 +201,21 @@ class lt_bus : public sc_core::sc_module {
 
   // -- COMPUTE ABSOLUTE MEMORY MAP ADDRESS ------------------------------------
 
-  static range compute_abs_mmap_address(range rel, range map) {
+  static range compute_abs_mmap_address(range rel, range mmap) {
     // Compute absolute start address.
-    const sc_dt::uint64 abs_start = map.start + rel.start;
+    const sc_dt::uint64 abs_start = mmap.start + rel.start;
     // Start address must be in bounds of the memory map mapping.
-    assert(abs_start <= map.end);
+    assert(abs_start <= mmap.end);
 
     // Compute absolute end address. Limit by memory map if range exceeded.
-    const auto comp_abs_end = [&map](sc_dt::uint64 abs_end) -> sc_dt::uint64 {
-      if (abs_end > map.end /* exceeds mapping */ ||
-          abs_end < map.start /* wraps around */) {
-        return map.end;
+    const auto comp_abs_end = [&mmap](sc_dt::uint64 abs_end) -> sc_dt::uint64 {
+      if (abs_end > mmap.end /* exceeds mapping */ ||
+          abs_end < mmap.start /* wraps around */) {
+        return mmap.end;
       }
       return abs_end;
     };
-    const sc_dt::uint64 abs_end = comp_abs_end(map.start + rel.end);
+    const sc_dt::uint64 abs_end = comp_abs_end(mmap.start + rel.end);
 
     return range{abs_start, abs_end};
   }