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authorJohannes Stoelp <johannes.stoelp@gmail.com>2025-04-09 23:48:02 +0200
committerJohannes Stoelp <johannes.stoelp@gmail.com>2025-04-09 23:48:02 +0200
commit14137fe1e078d1eda7bf923ec1268e9f0c789c9a (patch)
tree5aca66fdf91e2b273c1acf5601e7a5ecede20305 /roles/webserver/files/www/memzero/pub
parenta05c5dc17ff4b5786dbeafca6ed0f8955f5ad581 (diff)
downloadansible-memzero-14137fe1e078d1eda7bf923ec1268e9f0c789c9a.tar.gz
ansible-memzero-14137fe1e078d1eda7bf923ec1268e9f0c789c9a.zip
nginx: intel vol4
Diffstat (limited to 'roles/webserver/files/www/memzero/pub')
-rw-r--r--roles/webserver/files/www/memzero/pub/.gen.sh1
-rw-r--r--roles/webserver/files/www/memzero/pub/references.html4
2 files changed, 5 insertions, 0 deletions
diff --git a/roles/webserver/files/www/memzero/pub/.gen.sh b/roles/webserver/files/www/memzero/pub/.gen.sh
index 6131b8d..f591ddd 100644
--- a/roles/webserver/files/www/memzero/pub/.gen.sh
+++ b/roles/webserver/files/www/memzero/pub/.gen.sh
@@ -110,6 +110,7 @@ emit "x86" arch/intel/intel64-optimization-ref-vol2.pdf https://cdrdv2.intel.
emit "x86" arch/intel/intel64-vol1-architecture-manual.pdf https://cdrdv2.intel.com/v1/dl/getContent/671436
emit "x86" arch/intel/intel64-vol2-instruction-ref.pdf https://cdrdv2.intel.com/v1/dl/getContent/671110
emit "x86" arch/intel/intel64-vol3-system-programming.pdf https://cdrdv2.intel.com/v1/dl/getContent/671447
+emit "x86" arch/intel/intel64-vol4-msr-registers.pdf https://cdrdv2.intel.com/v1/dl/getContent/671098
emit "riscv" arch/riscv/rv-1-unprivileged-isa.pdf https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC
emit "riscv" arch/riscv/rv-2-privileged-architecture.pdf https://github.com/riscv/riscv-isa-manual/releases/tag/Priv-v1.12
diff --git a/roles/webserver/files/www/memzero/pub/references.html b/roles/webserver/files/www/memzero/pub/references.html
index 4577e79..8beb69d 100644
--- a/roles/webserver/files/www/memzero/pub/references.html
+++ b/roles/webserver/files/www/memzero/pub/references.html
@@ -125,6 +125,10 @@
<a style="color:black;" href="/pub/arch/intel/intel64-vol3-system-programming.pdf">arch/intel/intel64-vol3-system-programming.pdf</a>
[<a href="https://cdrdv2.intel.com/v1/dl/getContent/671447">original</a>]
</li>
+ <li class="content x86">
+ <a style="color:black;" href="/pub/arch/intel/intel64-vol4-msr-registers.pdf">arch/intel/intel64-vol4-msr-registers.pdf</a>
+ [<a href="https://cdrdv2.intel.com/v1/dl/getContent/671098">original</a>]
+ </li>
<li class="content riscv">
<a style="color:black;" href="/pub/arch/riscv/rv-1-unprivileged-isa.pdf">arch/riscv/rv-1-unprivileged-isa.pdf</a>
[<a href="https://github.com/riscv/riscv-isa-manual/releases/tag/Ratified-IMAFDQC">original</a>]