asm: add inc, xor insn and initial support for memory base+idx

3 files changed, 34 insertions, 0 deletions

diff --git a/src/insn/add.rs b/src/insn/add.rs
index b8fe96c..d5312be 100644
--- a/src/insn/add.rs
+++ b/src/insn/add.rs
@@ -13,6 +13,12 @@ impl Add<Reg32, Reg32> for Asm {
     }
 }
 
+impl Add<MemOp, Reg64> for Asm {
+    fn add(&mut self, op1: MemOp, op2: Reg64) {
+        self.encode_mr(0x01, op1, op2);
+    }
+}
+
 impl Add<MemOp, Reg16> for Asm {
     fn add(&mut self, op1: MemOp, op2: Reg16) {
         self.encode_mr(0x01, op1, op2);
@@ -24,3 +30,9 @@ impl Add<MemOp, Imm16> for Asm {
         self.encode_mi(0x81, 0, op1, op2);
     }
 }
+
+impl Add<Reg64, MemOp> for Asm {
+    fn add(&mut self, op1: Reg64, op2: MemOp) {
+        self.encode_rm(0x03, op1, op2);
+    }
+}
diff --git a/src/insn/inc.rs b/src/insn/inc.rs
new file mode 100644
index 0000000..ede780a
--- /dev/null
+++ b/src/insn/inc.rs
@@ -0,0 +1,14 @@
+use super::Inc;
+use crate::{Asm, Reg32, Reg64};
+
+impl Inc<Reg64> for Asm {
+    fn inc(&mut self, op1: Reg64) {
+        self.encode_r(0xff, 0, op1);
+    }
+}
+
+impl Inc<Reg32> for Asm {
+    fn inc(&mut self, op1: Reg32) {
+        self.encode_r(0xff, 0, op1);
+    }
+}
diff --git a/src/insn/xor.rs b/src/insn/xor.rs
new file mode 100644
index 0000000..b1fdc48
--- /dev/null
+++ b/src/insn/xor.rs
@@ -0,0 +1,8 @@
+use super::Xor;
+use crate::{Asm, Reg64};
+
+impl Xor<Reg64, Reg64> for Asm {
+    fn xor(&mut self, op1: Reg64, op2: Reg64) {
+        self.encode_rr(&[0x31], op1, op2);
+    }
+}